US 4,400,693 AGranted

MOS Parallel A/D converter

AssigneeITT Industries, Inc.

InventorPeter M. Flamm

Life of this patent

Estimating the term…

Loading patent…

Abstract

For the dynamic compensation of the offset voltage in such converters each non-inverting comparator input (+) is connected via a first transfer transistor (T11, T12, T1p) to the signal input (SE) and via a second transfer transistor (T21, T22, T2p) to the associated voltage divider tap of the voltage divider as applied to the reference voltage (Ur). Moreover, each inverting comparator input (-), via capacitor (C1, C2, Cp) is applied to the associated voltage divider tap and, via a third transfer transistor (T31, T32, T3p) and across a resistor (R'1, R'2, R'p) arranged in series therewith, to the associated comparator output. The second and third transfer transistors are rendered conductive during short intervals (T) between conversions by the clock signal (F), and the first transfer transistors are rendered non-conductive via the inverter (IV), and during the conversion time (t) the first transfer transistors are rendered conductive, and the second and third transfer transistors are rendered non-conductive. In television receivers, such MOS parallel A/D converters are suitable for processing the video signal, in which case the line sweep period serves as the conversion time (t), and the line fly-back period serves as the interval (T) between conversions.

Claims2

Dependent claims

Monolithic integrated parallel analog-to-digital converter (MOS parallel A/D converter) employing insulated-gate field-effect transistors, comprising p=2.sup.n -l comparators (K1, K2, Kp), a voltage divider applied to a reference voltage (Ur), consisting of p or p-1 resistors (R1, R2, Rp), and a decoder part (DC) connected to the outputs of said comparators, with n being indicative of the number of binary positions of the digital converter output signal, and with all comparator inputs of the one kind (+) being coupled to the signal input (SE) and with the comparator inputs of the other kind (-) being coupled to one voltage divider tap each, characterized by the following features:

each non-inverting comparator input (+) is applied via the controlled current path of a first transfer transistor (T11, T12, T1p) to the signal input (SE) and, via the controlled current path of a second transfer transistor (T21, T22, T2p) to the associated voltage divider tap,
each inverting comparator input (-) is applied via a capacitor (C1, C2, Cp) to the associated voltage divider tap,
each comparator output is applied across a resistor (R'1, R'2, R'p) and via the controlled current path of a third transfer transistor (T31, T32, T3p) as arranged in series therewith, to the inverting comparator input (-),
the gates of the second and of the third transfer transistor (T21, T31;
T22, T32;
T2p, T3p) are connected with each other and are applied to a clock signal (F) by which they are rendered conductive only during a short interval (T) between conversion, and
the gates of said first transfer transistors (T11, T12, T1p) are applied to said clock signal (F) via an inverter (IV).

4 more elements

Dependencies are inferred from the claim text.