US 4,400,667 A · Phase tolerant bit synchronizer for digital signals

Abstract

A bit synchronizer for digital data signals capable of tracking phase errors of up to .+-.180.degree. without loss of lock. An input data signal is squared and then applied to a pair of D-type flip-flops. The flip-flops are alternately driven by a clock signal generated by a voltage controlled oscillator in a phase-locked loop. The flip-flops cause the input data to be shifted 0.degree. and 180.degree., respectively, with reference to the clock signal. The flip-flops are cross-coupled to a pair of exclusive-OR gates, in a manner such that as the phase error between the input signal and the clock signal increases or decreases, the pulse width out of one gate varies proportionately while the output of the other gate is a pulse which is always one-half the clock signal period. The phase relationship of the pulses out of the gates switch 180.degree. as the phase error traverses the 0.degree. point. The outputs of the gates are summed to provide a measure of the phase error between the clock signal and the input signal and to produce a net control voltage representative thereof. The control voltage is applied to the oscillator to cause the frequency and phase of the clock signal generated thereby to be synchronous with that of the input signal. In the absence of bit transitions, the phase-locked loop is biased to seek the tuned bit rate. The described arrangement permits tracking phase errors over a .+-.180.degree. range without loss of synchronization.

Claims16

Dependent claims

Apparatus for generating a clock signal synchronous with the bit rate of a received data signal comprising:

voltage controlled oscillator means, said oscillator means generating a first clock signal whose frequency varies as a function of a net control voltage applied thereto;
means for generating a second clock signal shifted by 180.degree. from said first clock signal;
means responsive to said first and second clock signals and said received data signal, for respectively outputting first and second signals representative of said received data signal, said second signal being shifted by an amount proportional to the phase difference between said second clock signal and said received data signal, and said first signal being shifted by one-half bit period from said second signal;
means responsive to said received data signal and said first data representative signal, for producing a first output signal having a variable width proportional to the phase difference between said received data signal and said first clock signal;
means responsive to said second data representative signal and the complement of said first data representative signal, for producing a second output signal having a fixed width of one-half bit period;
and
means for summing said output signals to generate a net control voltage which is applied to said oscillator means, whereby the frequency and phase of said first clock signal is synchronized with that of said received data signal.

4 more elements

Apparatus for generating a clock signal synchronous with the bit rate of a received data signal comprising:

phase-looked loop means including a loop filter, a loop amplifier, and a voltage controlled oscillator, said oscillator generating a first clock signal whose frequency varies as a function of a net control voltage applied thereto;
means for generating a second clock signal shifted by 180.degree. from said first clock signal;
first and second register means, each having inputs responsive to said received data signal and inputs responsive respectively to said first and second clock signals, each register outputting first and second signals representative of said received data signal and the logical complement of said received data signal, the output signals of said second register means being shifted by one-half bit period from the output signals of said first register means;
first and second phase error detecting means, said first phase error detecting means having an input responsive to said first output signal of said second register means and to said complementary signal output of said first register means whereby said first phase error detecting means produces an output signal having a fixed width of one-half bit period, said second phase error detecting means having an input responsive to said received data signal and to said first signal output of said first register means, whereby said second phase error detecting means produces an output signal complementary to said fixed width output signal and having a width proportional to the phase difference between said received data signal and said first clock signal;
and
means for summing said output signals of said phase error detecting means to generate a net control voltage which is applied to said phase-looked loop means, whereby the frequency and phase of said first clock signal is synchronized with that of said received data signal.

3 more elements

Dependencies are inferred from the claim text.

Phase tolerant bit synchronizer for digital signals

Life of this patent

Phase tolerant bit synchronizer for digital signals

Life of this patent

Abstract

Claims16