Fixed rate delay circuit

A fixed rate delay circuit, wherein an input pulse sequence having time varied pulse intervals is delayed sequentially at a fixed rate of one divided by an integer'th power of 2 of an immediately preceding pulse interval in order, comprising

• a binary counter for counting clock-pulses having a predetermined repetition interval every time prior to a reset signal applied thereto,
• a latch circuit for latching respectively every digit of a binary number of the clock-pulses counted by said binary counter in response to the input of a latch signal just preceding said reset signal,
• a timing pulse generator for generating said latch signal which consists of differential pulses corresponding respectively to each pulse of said input pulse sequence and for forming said reset signal by delaying said differential pulse by a time duration being shorter than the repetition interval of said clock-pulses,
• a plurality of exclusive OR gates, to respective first inputs of which every digit of said binary number of the clock-pulses counted by said binary counter is applied in order and to respective second inputs of which every digit of said binary number which is latched by said latch circuit is applied in order after being shifted down respectively by integral digits for deriving respective OR output signals when said every digit applied to the respective first inputs and every shifted down digit applied to the respective second inputs coincide with each other in order, and
• a NOR gate, to which the respective OR output signals of said plurality of exclusive OR gates are applied, for deriving said input pulse sequence after being delayed at said fixed rate.