Level detection circuit

A level detection circuit comprising:

• a peak value detection and holding circuit having a single capacitor and a diode, for detecting and holding the peak value of an input signal by charging said capacitor;
• operation control means for supplying said input signal to said peak value detection and holding circuit during a specific time interval to perform maximum peak value detection and holding operation, said maximum peak value occurring during said specific time interval;
• a discharge circuit for performing constant current discharge of the charge in said capacitor of said peak value detection and holding circuit, said discharge being initiated at a time point after said specific time interval;
• and
• means for providing an indication of a time point when the terminal voltage of said capacitor during discharge reaches a specific voltage whereby the level of said input signal can be determined by the value of the time interval between the time point when the constant current discharge of said capacitor is initiated and the time point when the terminal voltage of the capacitor reaches said specified voltage.