US 4,400,615 AGranted

Programmable counter circuit

AssigneeFujitsu Limited

InventorsFumitaka Asami, Osamu Takagi

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Abstract

In order to improve the operable frequency of a programmable counter circuit which serves as an N-step counter by loading an initial value N, load terminals of flip-flops of respective stages forming the counter circuit are sequentially cascade-connected via buffers and a load signal is applied to each of the load terminals from a load signal generator circuit. The load signal generator circuit includes a detector circuit which detects a specified value which is provided a short time before the initial value loading of the counter circuit and generates a detected output signal. The detected output signal is shifted by a shift register included in the load signal generator circuit which operates on the same clock signal as that which drives the counter circuit, thereby generating the load signal at the moment of the initial value loading of the counter circuit. In this case, for the duration of the load signal and a certain period of time subsequent thereto the application of the output from the detector circuit to the shift register is inhibited by a load control circuit included within the load signal generator circuit, thus preventing erroneous loading.

Claims11

Dependent claims

A programmable counter circuit, operatively connectable to receive a clock signal, comprising:

a counter circuit, operatively connectable to receive the clock signal, having stages, each stage including a flip-flop, each flip-flop having an output, in which an initial value including a specified value is loaded;
a buffer operatively connected to said counter circuit;
and
a load signal generator, operatively connected to said buffer, for generating a load signal which is applied by said load signal generator through said buffer to the flip-flop of each stage of said counter circuit and which loads the initial value into said counter circuit, so that said programmable counter circuit serves as an N-step counter dependent on the initial value loaded, wherein said load signal generator comprises:
a detector circuit, operatively connected to the output of each flip-flop of each stage of said counter circuit, for detecting the specified value which is provided a short time before the initial value loading of said counter circuit and for generating a detected output signal;
a shift register, operatively connected to said detector circuit and operatively connectable to receive the clock signal, said shift register shifting upon reception of the detected output signal from said detector circuit, the shifting controlled by the same clock signal as that for driving the counter circuit and said shift register generating the load signal at the moment of the initial value loading of the counter circuit;
and
a load control circuit, operatively connected to said counter circuit, for sending out a load inhibit signal and for preventing the application of the output from the detector circuit to said shift register for the duration of the load signal and a predetermined period of time subsequent to the load signal.

5 more elements

A programmable counter circuit, operatively connectable to receive an initial value, comprising:

counter means, operatively connectable to receive the initial value, for loading the initial value and counting a number of times equal to the initial value and for generating flip-flop signals having a first level and a delayed load signal;
and
load signal generation means, operatively connected to said counter means, for generating only one load signal each time said counter means counts for the number of times equal to the initial value, whereby said counter loads the initial value when the load signal is output by said load signal generation means, said load signal generation means comprising:
a shift register circuit, having a first input and having an output operatively connected to said counter means, for generating the load signal;
a load control circuit, having first, second and third inputs operatively connected to said counter means, having a fourth input operatively connected to the output of said shift register circuit, and having an output, for receiving the flip-flop signals, and for generating a load inhibit signal having a first level whenever the delayed load signal is detected and for a predetermined period after detecting the load signal;
and
a count value detector circuit, having data inputs each operatively connected to said counter means, having an inhibit input operatively connected to the output of said load control circuit, having an output operatively connected to the first input of said shift register, for generating a detection signal whenever all of the flip-flop signals received by said count value detector circuit are of the first level and the load inhibit signal is of the first level, so that only one load signal is generated each time said counter means counts for the number of times equal to the initial value.

4 more elements

Dependencies are inferred from the claim text.