Monolithic integrated circuit
AssigneeNippon Electric Co., Ltd.
InventorHajime Masuda
Life of this patent
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Abstract
In a semiconductor memory device of the type having PNPN elements for transferring checking and programming currents to a memory cell, and a trigger circuit for activating the PNPN elements at a predetermined potential, a voltage limiting circuit is provided to activate the PNPN elements prior to achieving the triggering potential so that large voltage spikes through the memory elements during the memory checking operation can be prevented.
Claims12
An integrated circuit comprising a plurality of memory cells each having a PN junction for storing binary coded information in accordance with whether said PN junction is destroyed or not, supplying means for supplying a programming current for destroying said PN junctions, said supplying means having a parasitic capacitance, selecting means for selecting at least one memory cell, transferring means coupled to said supplying means and said memory cell selected by said selecting means for transferring said programming current to the selected memory cell, and control means coupled to said transferring means for suppressing an accumulation of an undesired charge in said parasitic capacitance, whereby a large current due to said undesired charge is prevented from flowing through said selected memory cell.
A monolithic integrated circuit formed on a semiconductor chip comprising a memory cell having a PN-junction and coupled to a row line and a column line, means for selecting said row line and said column line in response to an address signal, an address terminal receiving said address signal, means for supplying a programming current to said PN-junction of said memory cell, a programming circuit having a PNPN element and transferring said programming current to said PN junction, said PN-junction being destroyed by said programming current, means for selecting said programming circuit in response to said address signal, an output circuit coupled to said column line and transferring said programmed information in said memory cell to an output terminal, a voltage clamp circuit coupled to an N-type region in the first stage of said PNPN element for activating quickly said PNPN element of said programming circuit by triggering at a first potential, and a voltage limiter circuit for holding said N-type region of said PNPN element at a second potential that is lower than said first potential during a predetermined period.
A combination comprising a plurality of memory cell blocks storing programmed data therein, each block including a plurality of memory cells, output circuits coupled to said memory cell blocks, respectively, for reading out said programmed data to a plurality of output terminals, means for selecting one memory cell in each block, a plurality of programming circuits for programming said data in selected memory cell by supplying a programming current, said programming circuits being coupled to said output terminals, respectively, a voltage clamp circuit for triggering said programming circuits with a first potential, and a voltage limiter circuit for holding said programming circuit at a second potential that is lower than said first potential during a predetermined period.
A monolithic integated circuit comprising a terminal through which a writing current and a checking current flow, a plurality of memory elements responsive to said writing current for storing information, transferring means coupled to said terminal and said memory elements for selectively transferring said writing current and said checking current from said terminal to said memory elements when activated, selectively activating means for selectively activating said transferring means, applying means provided separately from said selectively activating means and coupled to said transferring means for applying a predetermined voltage to said transferring means when activated, and limiting means coupled to said transferring means for limiting the voltage at said terminal to a value lower than said predetermined voltage.
Dependencies are inferred from the claim text.