Monolithically integrated semiconductor circuit

Method of operating a monolithically integrated semiconductor circuit with a signal input addressable by a first signal type, constituting analog signals, and with a signal output delivering a second signal type constituting digital signals, the circuit including a circuit section for converting the analog signals of the first signal type into the digital signals of the second signal type, said circuit section having a charge transport circuit forming an analog adder, the signal input addressable by an analog signal being connected via a sampler and a low-pass filter to a first MOS capacitor operated as a sample-and-hold member;

• a second MOS capacitor connected to a third MOS capacitor connected, in turn, to a charge source, said first MOS capacitor and said third MOS capacitor having respective probes for determining the surface potential and for addressing a first comparator;
• said first capacitor being connected to a fourth MOS capacitor which, in turn, is connected to said analog adder, said second MOS capacitor being connected to a fifth MOS capacitor which, in turn, is connected to said analog adder;
• said fourth and said fifth MOS capacitors having surface potentials serving for controlling a second comparator, said fourth MOS capacitor being provided for controlling a third comparator, and said fifth MOS capacitor being provided for controlling a fourth comparator;
• said fourth and said fifth MOS capacitors having equal area, said area being markedly smaller than that of all of the other MOS capacitors including the MOS capacitors of said analog adder, which comprises, immediately after the arrival of each charge packet at the first MOS capacitor, connecting the gate of the third MOS capacitor to the gate of the first MOS capacitor and, through the charge source and the threshold located between the charge source and the third MOS capacitor, producing in the third MOS capacitor an amount of charge equal to the sum of twice the base charge and the mobile charge adjusting itself for maximum signal amplitude in the first MOS capacitor, and then, with the threshold between the second and the third MOS capacitor open to the second MOS capacitor, transferring the amount of charge corresponding to the base charge from the third to the second MOS capacitor while lowering the voltage at the gate electrodes of the first and third MOS capacitors, and while connecting the gate electrode of the second MOS capacitor to the original potential of the first MOS capacitor.