Back to results
US 4,399,517 AGranted
Multiple-input binary adder
AssigneeTexas Instruments Incorporated
InventorsJeffrey A. Niehaus, Kevin M. Ovens
Life of this patent
Estimating the term…
Abstract
An improved 6-input adder is disclosed. The adder decodes pairs of inputs to provide three sets of NAND, NOR and Exclusive OR terms which are inputted to AND-OR-INVERT arrays which generate first and second carry output terms of a 3-bit binary number in less than three gate delays.
Claims7
In an integrated circuit device, a circuit for adding a plurality of binary inputs of equal weight to generate sum, first carry and second carry output terms representing a 3-bit binary number, the circuit comprising:
- first circuit means responsive to the binary inputs for generating a plurality of intermediate output terms, the intermediate output terms including the NAND, NOR and Exclusive OR of first and second binary inputs and the NAND, NOR and Exclusive OR of third and fourth binary inputs;
- second circuit means responsive to selected combinations of the intermediate output terms for generating the sum output term;
- third circuit means responsive to selected combinations of the intermediate output terms and the binary inputs for generating the first carry output term;
- and
- fourth circuit means responsive to selected combinations of the intermediate output terms for generating the second carry output term.
2 more elements
Dependencies are inferred from the claim text.