Stored-program control machine
AssigneeBell Telephone Laboratories, Incorporated
InventorsDonald E. Blahut, Marc L. Harrison, Michael J. Killian, Mark E. Thierbach
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Abstract
A hierarchical organization of programmable logic arrays permits the control of microprocessor functions to be achieved in a way which allows otherwise wasted clock time to be used. The mostly independent operations of the several PLA's is organized by "handshake" signals from the latches of one PLA to those of another via AND circuits operative to selectively enable clock signals, in some instances, and data in other instances, to be applied to the latches. The use of the AND circuits enables requisite operations to be achieved with relatively small PLA's.
Claims10
An integrated circuit structure including a first logic array having an associated input register for supplying first signals to said first logic array, and a second logic array having an associated output register for receiving second signals from said second logic array, said input and output registers being operative respectively in response to first and second phase clock pulses, clock means for applying clock pulses in said first and second phase and means for applying inputs to said input register, said structure being characterized by control means connected between said output register and said input register responsive to an output from said output register during each second phase clock pulse for controlling modification of selected ones of said second signals received in the output register during the next preceding second phase clock pulse.
An integrated circuit structure including at least first and second PLA's with first decoder and first ROM sections and with second decoder and second ROM sections respectively, said first and second decoder sections having associated therewith first and second input registers respectively, said input registers including gates and being operative in a first phase of a clock cycle to latch data, said first and second ROM sections having associated therewith first and second output registers respectively, said output registers including gates operative in a second phase of a clock cycle to latch data, a clock means for providing clock pulses in first and second phases, and first control means connected between said second output register and said first input register responsive to a first output signal from said second output register during a second phase for selectively enabling input to said first input register in the next subsequent first phase.
A digital processor including first and second logic arrays having first input and output and second input and output registers, respectively, a first feedback path between at least said first output register and said first input register and means for electrically connecting an output of said second output register to an input of said first input register.
Dependencies are inferred from the claim text.