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AssigneeIBM Corporation
InventorsMichael R. Cosgrove, deceased, Alexander H. Frey, Jr., Kenneth A. Moore, Abraham Peled, Frederic N. Ris, William W. Sproul, III
Estimating the term…
An instruction pipeline for a data processor is disclosed, in which instruction execution is carried out in a sequence of phases which include fetching the instruction from an instruction storage, computing a data storage address from the fetched instruction, accessing the data storage at the computed address to obtain a datum operand, and then carrying out the logical or arithmetic operation on the accessed datum in accordance with the fetched instruction. Branch and stack instructions and return instructions are accommodated by providing a return address stack in the data storage, which stores the next instruction store address to be returned to after a return operation has been completed. Since the instruction address stack in the data storage cannot be directly accessed by the instruction fetching stage of the pipeline until several instruction execution phases have transpired, without degrading the performance of the pipeline, a stack register is provided in the instruction fetch stage of the pipeline which contains a duplicate of the instruction store address presently residing at the top of the instruction address stack. Then when a return instruction is encountered in the instruction fetch stage, the address of the next instruction to be returned to in the instruction storage is immediately available without interrupting the flow in the pipeline. A stack pointer in a stage of the pipeline between the instruction fetch stage and the data store access stage, then takes advantage of unused instruction phases in the pipeline, to cause the data store access stage to read the next available instruction store address from the instruction address stack therein and load it into the stack register in preparation for the next return instruction. Thus, the data storage and instruction stacking function can be shared in the same data storage device which is accessed by an intermediate stage in the multiple phase instruction pipeline without degrading the performance of the pipeline.
In a stored program data processor formed on an integrated circuit chip, having a pipelined instruction mechanism including four time-sequential stages with a first stage for instruction sequencing and fetch, a second stage for data store address generation, a third stage for data store access, and a fourth stage for arithmetic execution, said stages operating in an overlapped mode on successive instructions each including an op code and an operand, which are accessed from an instruction store external to said chip, to carry our arithmetic operations on data accessed from a data store external to said chip, an improved instruction branching mechanism, comprising:
In a stored program data processor formed on an integrated circuit chip, having a pipelined instruction mechanism including a plurality of time-sequential stages with a first stage for instruction sequencing and fetch, a second stage for data store address generation, and a third stage for data store access, said stages operating in an overlapped mode on successive instructions each including an op code and an operand, which are accessed from an instruction store external to said chip, to carry out operations on data accessed from a data store external to said chip, an improved instruction branching mechanism, comprising:
In a stored program data processor, at least a portion of which is formed on an integrated circuit chip, having a pipelined instruction mechanism including a plurality of time-sequential stages with a first stage for instruction sequencing and fetch, a second stage for data store address generation, and a third stage for data store access, said stages operating in an overlapped mode on successive instructions each including an op code and an operand, which are accessed from an instruction store external to said chip, to carry out operations on data accessed from a data store external to said chip, an improved instruction branching mechanism, comprising:
In a stored program data processor formed on an integrated circuit chip, having a pipelined instruction mechanism including a plurality of time-sequential stages with a first stage for instruction sequencing and fetch, a second stage for data store address generation, and a third stage for data store access, said stages operating in an overlapped mode on successive instructions each including an op code and an operand, which are accessed from an instruction store external to said chip, to carry out operations on data accessed from a data store external to said chip, an improved method for instruction branching, comprising the steps of:
In a stored program data processor having a pipelined instruction mechanism including a plurality of time-sequential stages with a first stage for instruction sequencing and fetch, a second stage for data store address generation, a third stage for data store access, and a fourth stage for arithmetic execution, said stages operating in an overlapped mode on successive instructions each including an op code and an operand, which are accessed from an instruction store to carry out arithmetic operations on data accessed from a data store, an improved instruction branching mechanism, comprising:
In a stored program data processor having a pipelined instruction mechanism including a plurality of time-sequential stages with a first stage for instruction sequencing and fetch, a second stage for data store address generation, and a third stage for data store access, said stages operating in an overlapped mode on successive instructions each including an op code and an operand, which are accessed from an instruction store to carry out operations on data accessed from a data store, an improved instruction branching mechanism, comprising:
In a stored program data processor having a pipelined instruction mechanism including a plurality of time-sequential stages with a first stage for instruction sequencing and fetch, a second stage for data store address generation, and a third stage for data store access, said stages operating in an overlapped mode on successive instructions each including an op code and an operand, which are accessed from an instruction store to carry out operations on data accessed from a data store, an improved instruction branching mechanism, comprising:
In a stored program data processor having a pipelined instruction mechanism including a plurality of time-sequential stages with a first stage for instruction sequencing and fetch, a second stage for data store address generation, and a third stage for data store access, said stages operating in an overlapped mode on successive instructions each including an op code and an operand, which are accessed from an instruction store to carry out operations on data accessed from a data store an improved method for instruction branching, comprising the steps of:
Dependencies are inferred from the claim text.