US 4,399,506 AGranted

Store-in-cache processor means for clearing main storage

AssigneeInternational Business Machines Corporation

InventorsCharles W. Evans, Frederick O. Flusche, Benedicto U. Messina, Ethel L. Richardson, James R. Robinson, Joseph A. Wetzel

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Abstract

Inhibit means prevents a store-in-cache (SIC) from requesting or receiving any line fetch from MS when a clear line (CL) command is issued by a CPU to main storage (MS). Two CPU modes are provided: (1) an initial storage validation mode and (2) an instruction processing mode. The system operator controls the first mode so that a CPU can execute the CL command during system initialization without any prior data fetch from MS. In the second mode, the CL command is executed as a component of a program instruction fetched from MS that can clear a block in main storage. In a multiprocessor (MP), the CL command by any CPU requests a line store of pad data into an addressed line in MS only after each other SIC copy directory is searched and any found conflicting line is invalidated. Line castout to MS is prohibited for a conflicting line found in a cache by the CS command, which would have been a normal operation for other types of CPU commands. After any line conflict is found for any other cache in the MP, the completion of the CL command is delayed by cancelling the line pad write request to MS. Then the IE repeatedly reissues the CL command until all found conflicting lines are invalidated. As soon as no conflict is found in any copy directory, the currently issued CL command is completed by not cancelling the pad data request to MS, so that pad bytes are then written into the line in MS.

Claims19

Dependent claims

Means for clearing an area in shared main storage (MS) in a data processing system having plural central processing units (CPUs), each CPU having a store in cache (SIC) with a CPU cache directory and SIC controls, comprising

means for inhibiting any line fetch for the SIC when a clear storage (CS) command is issued by the associated CPU to requested SIC controls to clear an addressed area in MS,
means for requesting MS to write over a MS area with a data value determined by the CS command,
a system controller (SC) connected to a plurality of CPUs for receiving storage and special commands issued by the SIC controls including a CS command issued by any connected CPU,
a plurality of copy directories being included in the SC, each copy directory being a copy of an associated CPU cache directory in a connected CPU,
SC means for simultaneously searching the plurality of remote copy directories (relative to the requesting CPU's copy directory) for a requested address in response to each received command requesting a directory search, including a CS command, to find any conflicting address,
conflict signalling means in the SC being actuated by the SC means finding any conflicting address in any remote copy directory for signalling a conflicting address with an invalidation signal to the associated remote CPU's SIC controls,
SC controls for communicating any invalidation signal to the requesting CPU's SIC controls to cancel the MS requesting means,
invalidation means with each SIC controls for invalidating any corresponding entry at the conflicting address in the associated remote CPU cache directory,
SC signalling means with the remote SIC controls for providing a confirmation invalidation signal to the associated SC means to invalidate the entry at the conflicting address found in the the associated remote copy directory, and
means for enabling the MS requesting means to write the requested data value over the MS area addressed by the CS command when the SC controls communicate to the requesting CPU SIC controls of the completion of invalidation for every conflicting entry in each remote CPU cache directory and associated copy directory,
the MS area being cleared by a single CS command being equal to the area in any SIC which may be invalidated by the CS command.

8 more elements

A multiprocessing (MP) system having a plurality of central processors (CPUs), each CPU having a store-in-cache (SIC) with an SIC directory and SIC controls, comprising:

CPU command means for sending CPU requests including clear storage (CS) requests to the associated SIC controls to request MS to write over a MS area with a data value determined by a CS command making a CS request,
inhibit means associated with a requesting CPU's SIC controls to inhibit any cache miss by the associated SIC directory in response to a CS request in order to prevent a line fetch or line castout from occurring in response to a CS request,
storage control (SC) means connected between an associated set of the CPUs in the MP and a MP system storage (MS),
copy directories provided in the SC means, each copy directory being a copy of an associated SIC directory for a CPU,
SC priority means in each SC means for priority serializing associated CPU requests from the connected set of CPUs,
search control means in each SC means connected with the SC priority means to control which request next searches the copy directories in the SC,
cross-interrogation (XI) means connected between the copy directories for transferring each CS request from a requesting CPU to the SC priority means, the SC priority means providing equal or higher priority to a CS request than other CPU requests, whereby high priority for the CS request causes searching in all remote copy directories to be synchronized in all SCs,
search control means for each copy directory to determine if the CS request exists as a conflicting entry in any remote copy directory,
conflict sensing means in the SC means actuated by a conflicting entry found by a search control means to provide a conflict signal to an associated SIC directory,
SC controls for communicating any conflict signal to the requesting CPU to cancel the CS command and its request to MS and to cause reissuance of the CS command by the requesting CPU command means,
invalidation means with each remote SIC controls being actuated by a conflict signal from the conflict sensing means to invalidate any conflicting entry in the associated remote SIC cache directory and in the associated copy directory without any corresponding castout,
the MS area addressed by the currently active CS command being cleared when the SC controls do not communicate any conflict signal to the requesting CPU to cancel the CS command so that the command completes with its write request to MS.

9 more elements

Means for clearing a line at a time in main storage (MS) in a data processing system having a central processor (CPU) with a store-in-cache (SIC) having a processor cache directory and cache control means, comprising:

cache control means for connecting the processor cache directory and SIC to the processor and MS,
command means for providing processor storage requests and a special clear line (CL) command to the cache control means, the CL command containing a MS line address to be cleared,
inhibit means associated with the cache control means to inhibit the processor cache directory from having any fetch from MS when the command means issues the CL command,
invalidating means in the cache control means operating to invalidate any line in the SIC having the MS line address without any castout of the line content,
whereby the CL command is sent to MS to overwrite the line in MS with pad data regardless of whether the line exists in the associated SIC.

2 more elements

Dependencies are inferred from the claim text.