Duty cycle monitor circuit
AssigneeGTE Automatic Electric Labs Inc.
InventorGerald M. Rinaldi
Life of this patent
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Abstract
A duty cycle monitor circuit which detects variations in the duty cycle of a monitored pulse by comparing its duty cycle with the pulse width of an external reference signal. A detection circuit detects the duty cycle variation of the monitored pulse after being periodically reset by the external reference signal. A storage circuit is clocked by the reference signal and operates to store the output signals of the detection circuit. Upon detection of a duty cycle failure the monitor can be cleared by external control or detection of a monitored pulse having a valid duty cycle.
Claims8
A duty cycle monitor circuit for use in a switching system, including a source of reference signal pulses of first and second polarities and a clock signal source normally operated to provide clock signal pulses having a pulse width greater than the pulse width of said reference signal pulses, and abnormally operated to provide clock signal pulses having positive and negative going edges and a pulse width narrower than the pulse width of said reference signal pulses, said duty cycle monitor circuit comprising:
- detection means connected to said reference signal source and said clock signal source, operated in response to a reference signal pulse of said first polarity and contemporaneously occurring first and second edges of a clock signal pulse to provide a duty cycle detected signal;
- said detection means further operated in response to each reference signal pulse of said second polarity to clear said duty cycle detected signal;
- and
- storage means connected to said detection means and to said reference signal source, operated in response to said reference signal pulse of said second polarity and said duty cycle detected signal to provide a duty cycle failure signal.
Dependencies are inferred from the claim text.