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US 4,399,377 AGranted
Selectively operable bit-serial logic circuit
AssigneeNational Research Development Corporation
InventorEdwin V. Jones
Life of this patent
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AssigneeNational Research Development Corporation
InventorEdwin V. Jones
Estimating the term…
A logic circuit arrangement providing logical operations on serial data. The clock-controlled arrangement can transfer data bits internally either unchanged or subject to selected logical action and can thereby perform combinational and sequential logic on data bits, or resultant outputs, transferred at different points in time. In one form using semiconductor techniques a circuit arrangement (FIG. 11) is operated by mode controls M and clock controls C to transfer data bits unchanged or subject to logical action from inputs D, D to outputs Q, Q. A return signal path providing a time interval (FIGS. 3 and 4) and a mode controlled forward signal path (FIGS. 3 and 4) form a typical arrangement in which each clock signal processes an input data bit.
A logic circuit for performing at least one selected logical action on supplied serial data bits to provide a data output signal, said circuit including:
A bistable circuit including first, second and third pairs of transistors, the transistors within a pair having their emitters connected together;
A logic circuit of the type responsive to serial input data and clock signals applied thereto, including a clock controlled gate including at least two input terminals and one output terminal for generating, in response to said clock signal, an output signal in accordance with the instantaneous states of input signals applied to said input terminals, the improvement wherein said clock controlled gate is also responsive to a mode control signal applied thereto and includes:
A logic circuit for performing logical actions on supplied serial data to provide a data output, including:
A bistable circuit including first and second pairs of transistors, the transistors within a pair having their emitters connected together, the collectors of a first transistor of each pair connected by a current path and arranged to share a first common load circuit, the collectors of a second transistor in each pair connected by a current path and arranged to share a second common load circuit, respective feedback paths between the collector of the first transistor of the first pair and the base of the second transistor of the first pair and between the collector of the second transistor of the first pair and the base of the first transistor of the first pair;
Dependencies are inferred from the claim text.