Fabrication method for high power MOS device

In a method of fabricating a high power MOS semiconductor device comprising the steps of:

• forming a pair of spaced substantially V-shaped grooves in a semiconductor substrate through both a high conductivity region of one conductivity type and a region of opposite type conductivity that surrounds a substantial portion of said high conductivity region of one conductivity type,
• forming a first insulating layer in said substantially V-shaped grooves,
• forming a second insulating layer in said substantially V-shaped grooves,
• forming a doped electrically conductive polysilicon gate electrode layer on the surface of said second insulating layer in each of said pair of substantially V-shaped grooves,
• forming a third insulating layer on said polysilicon gate electrode layer,
• forming an opening in said third insulating layer to expose a surface portion of said polysilicon gate electrode layer, and
• depositing electrical contacts to make separate source and drain connections to regions of said semiconductor substrate and to make separate electrical contact to said polysilicon gate electrode layer through said opening in said third insulating layer, one of said electrical contacts being located on said third insulating layer.