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US 4,398,287 AGranted
Digital switching over PAM bus system
AssigneeBell Telephone Laboratories, Incorporated
InventorDouglas A. Spencer
Life of this patent
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AssigneeBell Telephone Laboratories, Incorporated
InventorDouglas A. Spencer
Estimating the term…
In a PAM bus switching bus which normally handles analog voice signals, the different DC offsets caused by the different buffing, summing and distribution amplifiers cause no ill effects because DC voltages are not passed by the remainder of the support elements. However, when it is attempted to switch logic level DC signals through such a PAM bus network, the DC offset which is an indeterminate function of the particular switching path established, makes it impossible to establish a uniform slicing level. In the illustrative embodiment a uniform slicing level is achieved by clamping the summing bus of the PAM system during a preamble of the time slot, measuring the offset on the distribution bus and then applying the measured offset to compensate the distribution bus during the remainder of the time slot when the actual data signal is allowed to be applied to the summing bus.
An arrangement for establishing a uniform slicing level in a PAM bus time division switching system serving a plurality of ports and including means for defining a repetitive sequence of time slots, a summing bus for receiving a signal sample from one of said ports and a distribution bus for delivering said signal sample to one of said ports during each of said time slots, comprising
A digital data port for connection to a summing and distribution bus, said port having a transmit and a receive operational amplifier, a transmit time slot switch operable to connect the output of said transmit operational amplifier to said summing bus and a receive time slot switch operable to connect an input of said receive operational amplifier to said distribution bus, a clamping time slot switch operable prior to the operation of said transmit time slot switch for clamping said summing bus and a compensating time slot switch operable during the time said clamping time slot switch is operated for connecting said distribution bus to another input of said receive operational amplifier.
A digital data port for connection to a summing and distribution bus, said port having a transmit and a receive operational amplifier, a transmit time slot switch operable to connect the output of said transmit operational amplifier to said summing bus and a receive time slot switch operable to connect an input of said receive operational amplifier to said distribution bus, a clamping time slot switch operable prior to the operation of said transmit time slot switch for clamping said summing bus, a sample and hold circuit, and a compensating time slot switch operable during the time said clamping time slot switch is operated for connecting said sample and hold circuit between said distribution bus and an inverting input of said receive operational amplifier.
A digital data port for connection to a summing and distribution bus, said port having a transmit and a receive operational amplifier, a transmit time slot switch operable to connect the output of said transmit operational amplifier to said summing bus and a receive time slot switch operable to connect the non-inverting input of said receive operational amplifier to said distribution bus, side-tone suppression means connecting the output of said transmit operational amplifier to an inverting input of said receive operational amplifier, clamping time slot switch means operable prior to the operation of said transmit time slot switch for clamping said summing bus, and compensating time slot switch means operable during the time said clamping time slot switch means is operated for connecting said distribution bus to said inverting input of said receive operational amplifier.
A digital data port for placing a symmetrical data eye on the summing bus of a PAM bus system including a distribution bus connectable to said summing bus over any of a plurality of paths exhibiting different DC offsets, said data port comprising switch means opening and closing in accordance with a digital data stream, a transmit and a receive operational amplifier, a transmit time slot switch operable to connect the output of said transmit operational amplifier to said summing bus and a receive time slot switch operable to connect an input of said receive operational amplifier to said distribution bus, voltage divider means connected between switch means and an input of said transmit operational amplifier, a clamping time slot switch operable prior to the operation of said transmit time slot switch for clamping said summing bus, and a compensating time slot switch operable during the time said clamping time slot switch is operated for connecting said distribution bus to another input of said receive operational amplifier.
A port for serving a line or a trunk appearing in a PAM bus switching system including a summing and a distribution bus connectable to each other over any of a plurality of different paths exhibiting different DC offsets, said port comprising
A port for serving a line or a trunk appearing in a PAM bus switching system including a summing and a distribution bus connectable to each other over any of a plurality of different paths exhibiting different DC offsets, said port comprising
Dependencies are inferred from the claim text.