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US 4,398,268 AGranted
Semiconductor integrated circuit device
AssigneeFujitsu Limited
InventorKazuhiro Toyoda
Life of this patent
Estimating the term…
Abstract
An integrated injection logic (I.sup.2 L) memory where sink currents flowing into non-selected memory cells are supplied from clamp circuits, not from the selected memory cell. In addition, the potential of the selected bit line through which a write current flows is decreased by the clamp circuits.
Claims6
A semiconductor integrated circuit device comprising:
- a plurality of word lines;
- a plurality of word drivers, each connected to one of said word lines;
- a plurality of hold lines;
- a plurality of pairs of bit lines, each bit line having a variable potential and each bit line pair selectively conducting an associated current including a sink current;
- a plurality of bit drivers, each connected to a corresponding pair of said bit lines;
- a plurality of memory cells of integrated injection logic, each connected to a corresponding one of said word lines, to a corresponding one of said hold lines and to a corresponding pair of said bit lines,
- each memory cell including:
- injectors comprising first and second transistors of a first conduction type which have a common emitter connected to said corresponding one of said word lines;
- a flip-flop comprising cross-coupled third and fourth transistors of a second conduction type, connected to said first and second transistors respectively, and an emitter connected to the corresponding pair of said bit lines;
- fifth and sixth transistors of a second conduction type, each comprising a base and a collector both connected in parallel with said third or fourth transistor, respectively and an emitter connected to the corresponding pair of said bit lines;
- said third, fourth, fifth and sixth transistors being connected to the corresponding one of said hold lines;
- and
- first clamp means for selectively raising the potential of a first bit line of each of said pairs of bit lines above that of the second bit line of each of said pairs of bit lines in response to a write enable signal and an input data signal, and for absorbing the sink current associated with each of said first bit lines.
10 more elements
A semiconductor integrated circuit device comprising:
- a plurality of word lines;
- a plurality of word drivers, each connected to one of said word lines;
- a plurality of hold lines;
- a plurality of pairs of bit lines, each bit line having a variable potential and each bit line pair selectively conducting an associated current including a sink current;
- a plurality of bit drivers, each connected to a corresponding pair of said bit lines;
- a plurality of memory cells of integrated injection logic, each connected to a corresponding one of said word lines, to a corresponding one of said hold lines and to a corresponding pair of said bit lines,
- each memory cell including:
- injectors comprising first and second transistors of a first conduction type which have a common emitter connected to said corresponding one of said word lines;
- a flip-flop comprising cross-coupled third and fourth transistors of a second conduction type, connected to said first and second transistors respectively, and an emitter connected to the corresponding pair of said bit lines;
- fifth and sixth transistors of a second conduction type, each comprising a base and a collector both connected in parallel with said third or fourth transistor, respectively, and an emitter connected to the corresponding pair of said bit lines;
- said third, fourth, fifth and sixth transistors being connected to the corresponding one of said hold lines;
- and
- clamp means for raising the potentials of non-selected pairs of said bit lines from that of a selected pair, and for absorbing the sink current associated with said non-selected pairs of bit lines, said selected pair being selected by said bit drivers.
10 more elements
Dependencies are inferred from the claim text.