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US 4,398,265 AGranted
Keyboard and display interface adapter architecture
AssigneeMotorola, Inc.
InventorsLarry C. Puhl, Lawrence E. Connell
Life of this patent
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AssigneeMotorola, Inc.
InventorsLarry C. Puhl, Lawrence E. Connell
Estimating the term…
A unique interface adapter is coupled to a microprocessor by a three-wire self-clocking serial data bus for accommodating a twenty-key keyboard and an eight-digit display. The interface adapter includes circuitry for recovering a clock signal and a non-return-to-zero (NRZ) data signal from the data signal transmitted on two forward signal lines of the serial data bus. The NRZ data signal is shifted into a receiving register, where address circuitry decodes the address portion of the data signal to provide a chip select signal and control circuitry decodes the control portion of the data signal to provide a register select signal, read/write signal and bus sense signal. The register select signal determines whether a control register or display register is to be loaded in response to the read/write signal with the data portion of the data signal. The control register signals activate four status indicating LED's, apply power to the display, select between a ten or sixteen digit display, enable an audio tone generator and reset a status bit flip-flop. The display register receives two BCD digits which are stored in a display memory. The keys of the keyboard are scanned at the same time digits read-out from the display memory are being applied to the display. The signals identifying the row and column of activated keys are provided in a return signal line of the serial data bus.
Interface adapter circuitry coupled to a plurality of input signals to a display having a plurality of display elements and further coupled to a self-clocking serial data bus having binary first and second forward data signal lines for receiving a binary data signal including data, address and control portions, transmitted from a signal source, the first and second forward data signals transmitted respectively on the first and second forward data signal lines having a first binary state before and after the data signal, the first forward data signal having a second binary state and the second forward data signal having the first binary state for data signal bits having a binary one state, the first forward data signal having the first binary state and the second forward data signal having the second binary state for data signal bits having a binary zero state, and the first and second forward data signals having the second binary state between successive data signal bits, said interface adapter circuitry comprising:
Dependencies are inferred from the claim text.