Image processing architecture

Apparatus for processing sequentially applied signals which are representative of a matrix of pixels to provide output signals useful for determining predetermined uncentered statistical moments associated with a predetermined pixel of said matrix, said output signals being derived from computations performed on a submatrix of pixels centered around said predetermined pixel which sequentially steps through said matrix in a manner such that each pixel in said matrix has said output signals computed therefore during each scan of said matrix, said predetermined moments being determined from the equation Mk=1/N.SIGMA.(x.sub.i -x).sup.k, where N is the total number of pixels in a submatrix of said matrix which is used to determined said output signals, x.sub.i is a signal indicative of a pixel in said submatrix, x is the mean of signals indicative of the pixels in said submatrix, and k is a particular moment, and wherein the first moment is given by M1=1/N.SIGMA.x.sub.i, said apparatus determining said output signals when a new sequentially applied signal is encountered and a corresponding predetermined pixel is encountered during each scan, said apparatus comprising:

• (a) a first processing section including a first set of means comprising:
• (i) first means for storing first signals indicative of respective columnar sums of signals located in a predetermined set of rows of said matrix associated with said predetermined pixel;
• (ii) second means for storing second signals indicative of the sum of a predetermined subset of columnar sums of said predetermined set of rows of said matrix;
• (iii) third means for storing third signals indicative of a predetermined pixel associated with a first predetermined column of said predetermined subset of columnar sums;
• (iv) fourth means for providing said first signals which are indicative of the sum of a first predetermined one of said first signals and said third signals, minus a predetermined one of said stored third signals, said fourth means providing said first signals to said first means so as to update said predetermined columnar sums stored thereby;
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• (v) fifth means for providing said second signals which are indicative of said sum of a predetermined subset of columnar sums and said first signals minus a second predetermined one of said stored first signals indicative of a second predetermined columnar sum of said predetermined subset of columnar sums, said fifth means providing said second signals to said second means so as to update said sum of a predetermined subset of columnar sums stored thereby, said second signals being provided as said output signals of said apparatus and which are indicative of the first uncentered moment of said submatrix.

An image processing system for processing a plurality of signals, each of said signals being indicative of a corresponding pixel within a pixel matrix array, said signals being successively applied to said system in a predetermined order, said system comprising:

• (a) a first processing section including:
• (i) a first storage register for storing a plurality of said applied signals corresponding to a first submatrix of said matrix array, said first submatrix includes the pixels located in all of the columns and given number of rows of said matrix;
• (ii) a second storage register for storing signals that are indicative of the columnar sums of said signals corresponding to the pixels of said first submatrix;
• (iii) a third storage register for storing an output signal indicative of the sum of a given subset of said columnar sums, said output signal thereby being indicative of the sums of the signals corresponding to a second submatrix of pixels, and second submatrix including all of the rows and a given number of columns of said first submatrix, said given number of columns corresponding to said given subset of columnar sums;
• (iv) a first summing circuit for generating updated columnar sum signals, each being indicative of the sum of one of said applied signals, one of said columnar sum signals stored in said second register, and the negative of one of said signals stored in said first register, said signals in each summation corresponding to a given one of the columns of said matrix, said updated columnar sum signals being applied to said second storage register;
• and
• (v) a second summing circuit for generating updated output signals, each being indicative of the sum of one of the updated columnar sums generated by said first summing circuit, said output signal stored in said third register, and the negative of one of said columnar sum signals stored in said second register, said updated columnar sum signals and said stored columnar sum signals in each summation corresponding to columns of said first submatrix that are respectively being included in and deleted from said second submatrix, said updated output signals being applied to said third storage register and further provided as output signals from said first processing section.