Data processing system having an instruction pipeline for processing a transfer instruction
AssigneeHitachi, Ltd.
InventorAkira Fujita
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AssigneeHitachi, Ltd.
InventorAkira Fujita
Estimating the term…
A transfer instruction to be executed by a data processor includes a first operand representing a transfer-in address and a second operand representing a transfer-out address. Since the number of bytes transferred at a time is determined by a particular data processor used, a plurality of number of transfers are required to transfer the total data bytes, and first and second operand addresses must be calculated for each transfer. In a pipeline controlled data processor in the present invention, a circuit for calculating the first operand address is separately provided and this circuit is utilized in the first operand address calculation for second and subsequent data transfer operation so that the address calculation step is completed in one cycle of the pipeline control.
In a data processing system capable of pipeline operation for parallelly executing instructions each consisting of a plurality of process steps including an operand address calculation step, said pipeline operation including the execution of a transfer instruction having a first operand field, a second operand field and a field (L) specifying the number of bytes to be transferred, wherein the transfer is carried out in a plurality of transfer operations, sequentially, such that a predetermined number of bytes are transferred at each transfer operation including first calculation means for calculating a second operand address in said operand address calculation step based on said second operand field;
In a data processing system capable of pipeline operation for parallelly executing instructions each consisting of a plurality of process steps including an operand address calculation step, said pipeline operation including the execution of a transfer instruction having a first operand field, a second operand field and a field (L) specifying the number of bytes to be transferred by transferring the bytes specified in said L field sequentially at a plurality of times with a predetermined number of bytes being transferred each time from storage locations starting from an operand address specified by the second operand to storage locations starting from an operand address specified by the first operand, including first calculation means for calculating a respective first and second operand address for each of said first and second operand fields in said operand address calculation step and for calculating a further second operand address which is said predetermined number higher per transfer than said calculated operand address based on said second operand field;
In a data processing system for executing a transfer instruction having a first operand field, a second operand field and a field (L) for specifying the number of bytes to be transferred and including a plurality of means adapted to operate independently of each other for executing different processing steps at the same time, said plurality of means comprising:
In a data processing system responsive to a transfer instruction having a first operand field, a second operand field and a field (L) for specifying the number of bytes to be transferred for transferring a number of data bytes specified by said L field at a time, from storage locations starting from a second operand address specified by the second operand field to storage locations starting from a first operand address specified by the first operand field of the transfer instruction, and including a plurality of means operative independently of each other for executing different process steps at the same time, said plurality of means comprising:
In a data processing system for executing a transfer instruction having a first operand field, a second operand field and a field (L) for specifying the number of bytes to be transferred, the improvement comprising;
In a data processing system for executing a transfer instruction having a first operand field, a second operand field and a field (L) for specifying the number of bytes to be transferred by transferring a number of data bytes specified by said L field, a predetermined number of bytes at a time, from storage locations starting from a second operand address specified by the second operand field to storage locations starting from a first operand address specified by the first operand field, the improvement comprising;
Dependencies are inferred from the claim text.