Interruptible microprogram sequencing unit and microprogrammed apparatus utilizing same
AssigneeFairchild Camera and Instrument Corporation
InventorsPaul Chu, James B. Klingensmith
Life of this patent
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AssigneeFairchild Camera and Instrument Corporation
InventorsPaul Chu, James B. Klingensmith
Estimating the term…
An interruptible microprogram sequencing unit (MSU) for providing a sequence of microinstruction addresses to a control memory containing microinstructions for the operation of a microprogrammed apparatus. The MSU includes an address output for providing microinstruction addresses to the control memory, an address bus connected to the address output such that a plurality of microinstruction addresses applied to the address bus are sequentially provided to the address output, means connected to the address bus for applying the plurality of microinstruction addresses to the address bus, an interrupt return register operably connected to the address bus for receiving a microinstruction address from the address bus and storing the received microinstruction address, and means connected to the address bus for interrupting the sequence of microinstruction addresses and effecting storage of a microinstruction address on the address bus in the interrupt return register.
An interruptible microprogram sequencing unit for providing a sequence of microinstruction addresses to a control memory which contains a plurality of microinstructions for the operation of a microprogrammed apparatus, the microprogram sequencing unit comprising:
A microprogrammed apparatus comprising a plurality of data paths for manipulating data, a control memory connected to said data paths for sequentially providing a plurality of addressable microinstructions contained in said memory to said data paths for controlling said data paths, and a microprogram sequencing unit connected to said control memory for providing a sequence of microinstruction addresses to said control memory, said microinstruction sequencing unit including an address output for providing addressing microinstruction addresses to said control memory, an address bus connected to said address output such that a plurality of microinstruction addresses applied to said address bus are sequentially provided to said address output, means connected to said address bus for applying said plurality of microinstruction addresses to said address bus, an interrupt return register operably connected to said address bus for receiving a microinstruction address from said address bus and storing said received microinstruction address, and means connected to said address bus for interrupting said sequence of microinstruction addresses and effecting storage of a microinstruction address on said address bus in said interrupt return register.
Dependencies are inferred from the claim text.