Data processing system having a unique instruction processor system

In a data processing system, an instruction processor means for decoding a plurality of first instructions forming a first designated basic instruction set the addresses of which have a first selected number of bits and a plurality of second instructions forming a second designated extended instruction set the addresses of which have a second selected number of bits different from said first selected number, each of said first or second instructions including at least an operating code portion which includes a selected bit code combination which identifies whether said instruction is from said basic instruction set or from said extended instruction set and some of said first and second instructions further including at least one displacement portion, said instruction processor means comprising

• instruction decode register means having at least two register regions, a first of said regions designated to temporarily store said operating code portion of an instruction and said at least one other region designated to temporarily store a displacement portion;
• means for supplying an incoming instruction of said basic instruction set or said extended instruction set;
• instruction decode shifter means connected to said instruction supplying means and responsive to said incoming instruction for entering said incoming instruction into said instruction decode register means so that said first designated region temporarily stores the operating code portion thereof and said at least one other designated region, if required, temporarily stores a displacement portion thereof;
• means responsive to the selected bit code combination of each incoming instruction for identifying whether said instruction is from basic instruction set or from said extended instruction set;
• and
• means for decoding the operating code portion of said identified instruction supplied thereto from said instruction decode register means to produce a plurality of operating code descriptors associated with said decoded instruction and for producing a starting address of one or more microinstructions associated with said decoded instruction.