US 4,398,224 A · Time base correcting apparatus

Abstract

Time base correcting apparatus is provided for a digital signal supplied to such apparatus in the form of successive data blocks with each data block including plural data words. A memory is provided, having plural addressable storage locations, each adapted to store a respective data block. A write address generator generates write-in addresses to address particular storage locations into which the supplied data blocks are written; and an error detector detects whether the supplied data block contains an error. If no error is detected, a write-in circuit writes that data block into the addressed storage location; but if an error is detected, the data block is inhibited from being stored. An error store also is provided to store an error flag which is, for example, reset when the nono-erroneous data block is written into the addressed storage location, and is set when an error in that data block is detected. A read address generator generates read-out addresses to address those storage locations from which storage data blocks are read. When the contents of an addressed storage location are read out, the error flag associated with that data block is set regardless of its actual condition, thereby preventing subsequent re-use of the contents of that addressed storage location in the event that the data block stored therein is not replaced but is attempted to be re-read.

Claims19

Dependent claims

Time base correcting apparatus for correcting time base errors in a digital signal supplied thereto in the form of successive data blocks, each data block including at least plural data words and an error detecting word, said apparatus comprising memory means having plural addressable storage locations, each storing a respective data block;

write address generating means for generating write-in addresses to identify the particular storage locations into which the supplied data blocks are written;
error detecting means responsive to said error detecting word for detecting an error in a supplied data block;
write-in means for writing successive data blocks into those storage locations identified by said write address generating means in the absence of an error detected by said error detecting means and for inhibiting the writing of a data block into an identified storage location when an error in said data block is detected;
error store means for storing an error signal indicative of whether a supplied data block contains a detected error and has not been written into a respective storage location or does not contain a detected error and has been written into said respective storage location;
read address generating means for generating read-out addresses to identify particular storage locations from which a stored data block is read;
and read-out means for reading out the contents of a storage location identified by said read address generating means and for setting the error signal in said error store means to indicate that the contents of the storage location then read out by said read-out means contain a detected error notwithstanding the actual condition of said error signal.

3 more elements

Time base correcting apparatus for correcting time base errors in successive data blocks supplied thereto, each data block including a plurality of multi-bit words, comprising memory means having a plurality of addressable locations for storing respective data blocks;

error flag memory means having a plurality of compartments, each associated with a respective location in said memory means for storing an error flag indicative of an error present in a data block supplied to said time base correcting apparatus;
read address generating means for generating successive read-out addresses to identify corresponding storage locations and compartments from which a stored data block and a stored error flag, respectively, are read;
means for setting the error flag in the identified compartment to a predetermined condition;
write address generating means responsive at least in part to said read-out addresses for generating successive write-in addresses to identify corresponding storage locations and compartments into which a data block and an error flag, respectively, are to be written;
error detecting means for detecting an error in said supplied data blocks;
and write means for writing a data block into the storage location and for resetting the error flag in the compartment identified by said write address generating means only if an error is not detected in said data block.

3 more elements

Dependencies are inferred from the claim text.

Time base correcting apparatus

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Time base correcting apparatus

Life of this patent

Abstract

Claims19