MOS Digital-to-analog converter with resistor chain using compensating "dummy" metal contacts
AssigneeIntel Corporation
InventorsMarcian E. Hoff, Jr., John M. Huggins
Life of this patent
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Abstract
An MOS integrated circuit digital-to-analog converter employing a plurality of generally parallel resistance strings. Decoding means and switching means provide an analog output from the resistance strings, this output passes through only two switches. The resistance strings may be closely fabricated on a substrate, thereby reducing the effects of processing variations. A unique layout for the converter array minimizes the effects of masking misalignments.
Claims8
An MOS array disposed on a silicon substrate for converting a digital signal to an analog signal including:
- a first and second elongated, generally parallel, spaced-apart, doped regions in said substrate, each for forming a resistance means;
- a first and second, elongated, generally parallel, spaced-apart strips of polysilicon disposed between and parallel to said spaced-apart first and second regions, said first strip adjacent to said first region and said second strip adjacent to said second region;
- a first and a second conductive line disposed generally transverse to and insulated from said strips and said first and second regions, said conductive lines crossing said regions and said strips;
- third and fourth doped regions in said substrate disposed between said spaced-apart first and second strips, said third region being disposed below said first line and said fourth region being disposed below said second line;
- contact means for coupling said third doped region with said first line and for coupling said fourth region with said second line;
- whereby one of said first and second regions may be coupled to said lines through said third or fourth regions by applying a potential to one of said first and second strips.
An MOS array disposed on a silicon substrate for converting a digital signal to an analog signal including:
- a first, second, third, and fourth, generally parallel, spaced-apart strips of polysilicon disposed on said substrate;
- a first elongated, doped region for forming a first resistance means in said substrate, disposed between said first and second strips;
- a second elongated, continuous doped region for forming a second resistance means in said substrate, disposed between said third and fourth strips;
- third and fourth doped regions disposed between said second and third strips;
- a first elongated conductive line, disposed generally transverse to said first, second, third and fourth strips, said first line being disposed above said third region;
- a second elongated conductive line, disposed generally transverse to said first, second, third and fourth strips, said second line being disposed above said fourth region;
- and,
- contact means for electrically coupling said third region to said first line, and said fourth region to said second line;
- whereby one of said first and second resistance means may be selectively coupled to said lines by application of a potential to one of said second and third strips.
Dependencies are inferred from the claim text.