US 4,398,179 AGranted

Analog-to-digital converting circuit

AssigneeSony Corporation

InventorShinji Kaneko

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Abstract

An analog-to-digital converting circuit comprises an input, a clock signal circuit providing first and second clock signals having the same frequency but having a half-cycle phase difference therebetween; first and second analog-to-digital converting stages each having an input coupled to the converting circuit input for receiving an input analog signal, a control terminal for receiving a respective one of the first and second control clock signals, and an output providing an N-bit binary-coded digital signal representing the level of the input analog signal, each having a voltage quantizing interval of .DELTA.V; an output terminal; and a multiplexing circuit, such as a parallel-to-serial converter, for alternately applying to the output terminal the binary coded digital signals of the first and the second analog-to-digital converting stages. In order to achieve greater accuracy, an offset circuit is included to provide to one of the first and the second analog-to-digital converting stages an offset voltage, relative to the other of such stages, of 1/2 .DELTA.V.

Claims9

Dependent claims

An analog-to-digital converting circuit comprising input means for receiving an analog signal to be converted to digital form;

clock signal generating means for generating first and second control clock signals having the same frequency but having a half-cycle phase difference therebetween;
first and second analog-to-digital converting stages each having an input coupled to said input means for receiving the input analog signal, a control terminal for receiving a respective one of said first and said second control clock signals, and an output providing an N-bit binary coded digital signal representing the level of said analog signal, and each having a voltage quantizing step of .DELTA.V;
an output terminal;
multiplexing means for alternately applying to said output terminal the binary coded digital signals of said first and second analog-to-digital converting stages;
and offset means for providing to one of said first and second analog-to-digital converting stages an offset voltage, relative to the other of such stages, of 1/2.DELTA.V, such that the digital signals provided at said output terminal have an accuracy of 1/2.DELTA.V.

2 more elements

Dependencies are inferred from the claim text.