Test circuit for MOS devices

A test circuit having MOS transistors and accommodated on a substrate together with at least one further MOS-circuit, which test circuit comprises at least one test terminal, which test terminal is capable of being combined with terminals of the further circuit and by means of which one or more test signals of a polarity opposite to that of the normal supply voltage are selectively applied, the further circuit then supplying signals which are indicative of the operation of the further circuit, thereby enabling said further circuit to be tested, said test circuit comprising a first gate circuit having an output and a first and a second input, the first input being coupled to one test terminal and the second input receiving a test signal of the same polarity as that of the supply voltage but of an amplitude which is substantially higher than that of said supply voltage, by means of which the test circuit is rendered responsive to test signals of a polarity opposite to that of the normal supply voltage on said first input terminal.