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US 4,398,105 AGranted
Arbiter circuit
AssigneeSignetics Corporation
InventorPhilip J. Keller
Life of this patent
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Abstract
An arbiter circuit includes a latch made of two crosscoupled NAND gates, one of which is a Schmitt NAND gate, a difference detector, and two output NOR gates. The output of the latch is coupled to the difference detector and to one input of the NOR gates. The NOR gates receive another input from the difference detector. The difference detector is responsive to a voltage difference that exceeds one V.sub.BE, thereby blocking signals that originate in the latch during oscillating or metastable states of the latch, which may include rut pulses.
Claims4
An arbiter circuit, comprising:
- (a) first and second input terminals and first and second output terminals;
- (b) first and second cross-coupled NAND gates coupled to said first and second input terminals, respectively;
- (c) a difference detector gate coupled to the outputs of said cross-coupled NAND gates and responsive to a voltage difference exceeding a specified amount;
- (d) first and second NOR gates having their outputs coupled to said first and second output terminals, respectively;
- (e) means coupling a first input of each of said NOR gates to the output of said difference detector gate, and
- (f) means coupling the output of said first NAND gate to a second input of said first NOR gate and coupling the output of said second NAND gate to a second input of said second NOR gate.
3 more elements
Dependencies are inferred from the claim text.