Switched-capacitance amplifier, a switched-capacitance filter and a charge-transfer filter comprising an amplifier of this type

A switched capacitance filter comprising at least a filter cell constituted by capacitors and MOS transistors in series with a switched-capacitance amplifier, the output of the amplifier being connected to the cell in a feedback loop;

• the gain of the amplifier being between 1 and 2;
• said filter cell comprising four series-connected TMOS transistors each having a source and drain, the input being on the drain of the first transistor and the output being on the source of the last transistor;
• capacitors being connected between the sources of three of the transistors and ground and between the source of the other transistor and the output of the amplifier;
• said amplifier is constituted by a voltage multiplier, comprising n capacitors, periodically switched in parallel and in series by MOS type transistors operating in the switching mode, a single voltage from the filter cell charging simultaneously the n capacitors which are switched in parallel, and an amplified voltage being obtained between the end terminals of the n capacitors which are simultaneously switched in series and wherein the capacitors and the transistors of the filter cell and amplifier are integrated on the same semiconductor substrate.

A charge-transfer filter comprising:

• a semiconductor substrate;
• an insulating layer deposited on the substrate;
• electrodes deposited on the insulating layer and ensuring charge transfer in the semiconductor by application of given potentials;
• means for reading quantities of charges;
• a differential amplifier which receives the voltages delivered by means for reading and produces the output voltage of the filter;
• wherein this amplifier is constituted by a voltage multiplier comprising n capacitors, periodically switched in parallel and in series by MOS type transistors operating in the switching mode, a single voltage charging simultaneously the n capacitors only when they are switched in parallel and an amplified voltage being obtained between the end terminals of the n capacitors which are simultaneously switched in series and wherein the n capacitors and the transistors are integrated on the same semiconductor substrate;
• in the voltage multiplier a first group of transistors G1 carries out switching of the n capacitors in parallel and a second group of transistors G2 carries out switching of said capacitors in series, and wherein switching of both groups of transistors is initiated by two periodic signals .phi.1 and .phi.2 applied to the gates of the MOS transistors, said signals being such that the two groups of transistors are not simultaneously in the conducting state;
• and
• the drains and sources of n transistors of the first group G1 (FIG. 3;
• T11 to T1n) are connected between one of the terminals of each capacitors including the end terminal A, and an input E1 to which is applied said charging voltage VE+;
• n other transistors of the first group G1 (FIG. 3;
• T1 (n+1) to T1 (2n)) being connected between the other terminal of each capacitor including the end terminal B;
• and a second input E2 to which is applied said charging voltage VE-;
• the drains and sources of (n-1) transistors of the second group G2 (FIG. 3;
• T21 to T2 (n-1)) being connected between the terminals of two capacitors except for the end terminals A and B;
• and an nth transistor of the second group (T2n) being connected between the terminal B and a reference voltage VR for adjusting the offset voltage of the multiplier;
• thus said multiplier being differential.

A circuit comprising at least a filter cell constituted by capacitors and MOS transistors associated to an amplifier, wherein this amplifier is constituted by a voltage multiplier, comprising n capacitors, periodically switched in parallel and in series by MOS type transistors operating in the switching mode, a single voltage charging simultaneously the n capacitors which are switched in parallel and an amplified voltage being obtained between the end terminals of the n capacitors which are simultaneously switched in series and wherein the n capacitors and the transistors are integrated on the same semiconductor substrates, the gain of the multiplier is between 1 and 2;

• and in said voltage multiplier a first group of transistors G1 carries out switching of the n capacitors in parallel and a second group of transistors G2 carries out switching of said capacitors in series, and wherein switching of both groups of transistors is initiated by two periodic signals .phi.1 and .phi.2 applied to the gates of the MOS transistors, said signals being such that the two groups of transistors are not simultaneously in the conducting state;
• the drains and sources of n transistors of the first group G1 (FIG. 1, T11 to T1n) are connected between one of the terminals of each capacitor including the end terminal A and an input (E) to which is applied said charging voltage (VE);
• the drains and sources of (n-1) other transistors of the first group G1 (FIG. 1;
• T1 (n+1) to T1 (2n-1)) being connected between the other terminal of each capacitor and ground except for the end terminal B which is connected directly to ground;
• the drains and sources of (n-1) transistors of the second group G2 (FIG. 1;
• T21 to T2 (n-1)) being connected between the terminals of two capacitors except for the end terminals A and B;
• and a capacitor C20 connected between the end terminal A and B.