Universal timing array

In a timing and control network having clock means and in which branch address, branch condition, branch command, synchronization, terminal count input, terminal count output, count enable, parallel enter, L1, L2, H1 and H2 data, select, substate terminal count, no hold, state count enable, complemented parallel entry, uncomplemented parallel entry, state parallel entry and Q state signals are developed and utilized each through single line access, the improvement residing in a universal timing array, said universal timing array being comprised of a single, large scale, integrated circuit having

• a multiplicity of 2-bit counter means operating on said clock means, each said 2-bit counter means being controlled by parallel entry, first, second and third enable, and first and second terminal count input control signals, each said 2-bit counter means generating a terminal count output and first and second state Q signals,
• a parallel data entry multiplexer for each 2-bit counter means, each said multiplexer receiving L1, L2, H1 and H2 data signals and selecting either L1 and L2 or H1 and H2 data in response to a select signal for input to its associated 2-bit counter means,
• a branch and increment logic circuit operating on said clock means, said branch and increment logic circuit receiving synchronization, branch command, branch condition, substate terminal count and no-hold signals and outputting a state count enable signal, complemented and uncomplemented parallel entry signals and state parallel entry signals, and
• a branch and increment logic circuit input multiplexer, receiving first, second, third and fourth branch condition signals and first and second branch address signals, said branch and increment logic circuit input multiplexer selecting branch condition signals in response to said first and second branch address signals for input to said branch and increment logic circuit.