Method of fabricating self-aligned MOS devices and independently formed gate dielectrics and insulating layers

A method for fabricating an MOS device having a substrate, a gate electrode, an isolating layer over the gate electrode, a gate dielectric under the gate electrode, and a gate dielectric on the substrate adjacent the gate electrode wherein the thicknesses of the gate electrode and the two gate dielectrics can be individually and substantially independently controlled, comprising the steps of:

• forming a first gate dielectric over the substrate;
• then
• defining a gate electrode over the gate dielectric;
• then
• establishing an isolating layer over the gate electrode and over the gate dielectric not covered by the gate electrode, including differentially thermally growing said layer such that it is relatively thick on the top and sides of the gate electrode and relatively thin over the gate dielectric;
• then
• anisotropically etching the gate dielectric adjacent the electrode from the substrate but leaving a substantial portion of the isolating layer on the top and sides of the gate electrode;
• and then
• establishing a second gate dielectric over the portion of the substrate from which the dielectric has been etched, whereby the thicknesses of the gate dielectrics and gate isolating layer are individually controllable.

A method of fabricating, on a substrate, an MOS memory cell having a pair of access gates, a memory gate electrode, and a pair of source/drain regions, comprising:

• (1) providing an isolating layer over the substrate;
• (2) depositing and defining first and second access gates over the isolating layer;
• (3) growing an oxide layer over the tops and sides of the access gates and over the isolating layer such that the oxide over the top and sides of the access gates is relatively thick and the oxide over the isolating layer is relatively thin;
• (4) anisotropically etching the oxide layer and the isolating layer until the substrate is exposed except where covered by the access gates and their underlying isolating layer;
• (5) pattern defining a tunnel oxide, then a memory insulator and then a second oxide over the memory insulator, all between the first and second access gates;
• (6) providing a memory gate electrode over the second oxide;
• (7) providing a third oxide layer over the memory gate, over the oxide on the access gates and on the substrate in the area of intended source/drain regions;
• and
• (8) implanting and diffusing first and second source/drain regions beneath the third oxide.

A method of fabricating a memory cell structure on a substrate, comprising:

• (1) establishing a distinct arsenic implant region in the substrate for a memory cell capacitor;
• then
• (2) forming a first gate oxide over the substrate and the arsenic implant so as to form a memory cell capacitor;
• then
• (3) defining a first gate electrode over the gate oxide;
• then
• (4) differentially thermally growing an insulating oxide over the structure formed in steps 1-3 such that the insulating oxide is relatively thick on the tops and sides of the first gate electrode and relatively thin over the gate oxide;
• then
• (5) anisotropically etching the structure formed in steps 1-4 so as to remove the insulating oxide and the gate oxide from the substrate and leaving at least a substantial portion of the insulating oxide on the top and sides of the first gate electrode;
• then
• (6) establishing a second gate oxide over the etched portion of the substrate;
• (7) defining an interconnect over the insulating oxide and over the first gate electrode;
• (8) defining a second gate electrode over the second gate oxide;
• and
• (9) implanting source/drain regions in the substrate to form an access transistor for the memory cell capacitor.

A method of forming a CCD structure on a substrate, comprising:

• (1) establishing a first gate oxide on the substrate;
• (2) defining a first gate electrode on the first gate oxide;
• (3) thermally growing a first insulating oxide over the structure formed in steps 1 and 2 such that the insulating oxide on the sides and top of the gate electrode is relatively thick and the insulating oxide on the first gate oxide is relatively thin;
• then
• (4) anisotropically etching the structure formed in steps 1-3 so as to remove oxides over the substrate and substantially retain insulating oxide on the top and sides of the first gate electrode;
• (5) growing a second gate oxide over the bare substrate;
• (6) defining a second gate electrode over the second gate oxide such that the latter electrode overlaps the first gate electrode;
• (7) thermally growing a second insulating oxide over the previously formed structure such that the second insulating oxide is relatively thick over the top and sides of the second gate electrode and relatively thin over second gate oxide;
• then
• (8) anisotropically etching the structure thus formed to lay bare the substrate covered by the second gate oxide;
• and
• (9) providing additional gate oxides, overlapping gate electrodes and insulating layers as set forth in steps 5 through 7.