Time delay computer

A time delay computer means comprising:

• an up-down counter means,
• count up actuating means initiating count up from zero operation of said up-down counter at a first fixed frequency f.sub.1 in response to a first input signal, said count up actuating means comprising a first flip-flop means receiving said first input signal, a fixed frequency oscillator means generating a signal of frequency f.sub.1, and a first AND gate means, said first AND gate means receiving the output of said fixed frequency oscillator means and actuating count-up operation of said up-down counter in response to an enabling signal from said flip-flop means, and
• count down actuating means disabling said count up actuating means and initiating count down operation of said up down counter means at a second pre-selected frequency f.sub.2 in response to a subsequently received second input signal, there being a pre-selected ratio of the time interval between said first and second input signals and the time interval between said second input signal and an output signal generated by the said up-down counter means, said ratio being a function of said second pre-selected frequency f.sub.2, said up-down counter means further generating a count down actuating means disabling signal when the counter reaches zero, said count down actuating means comprising, a second flip flop means receiving said second input signal and said count down actuating means disabling signal and providing a disabling signal to said first flip flop means, a variable frequency oscillator means generating a signal of frequency f.sub.2, and a second AND gate means, said second AND gate means receiving the output of said variable frequency oscillator means and actuating count down operation of said up-down counter means in response to an enabling signal from said second flip flop means.