US 4,397,001 AGranted

Semiconductor memory device

AssigneeFujitsu Limited

InventorYoshihiro Takemae

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Abstract

A semiconductor memory device of a dynamic type, including a read/write circuit in a column circuit in which a data input pin and a data output pin are common. The read/write circuit comprises a data-output buffer (DOB) connected through a three-state circuit (Qa, Qb) to the common data input/output terminal (I/O), and a data write-in buffer of a dynamic type having a latching function and being connected between the common data input/output terminal and data buses, for providing latched data to the data buses. By utilizing a rise or a fall of a write enable signal or a column address strobe signal applied to the memory device, the three-state circuit is set to be a high impedance, and then, write data is latched into the data write-in buffer.

Claims8

Dependent claims

A semiconductor memory device of a dynamic type comprising a memory cell and a column circuit, operatively connected to said memory cell and operatively connectable to receive column driving signals, said column circuit including a read/write circuit for reading data from or writing data into said memory cell in response to the column driving signals, said read/write circuit comprising:

a common input/output terminal for inputting write data into or for outputting read data from said memory cell;
a data output buffer, operatively connected to said common input/output terminal, for receiving said read data from said memory cell and for generating control signals;
a three-state circuit, operatively connected to said common input/output terminal and to said data output buffer, for receiving said control signals and for generating and applying a first level signal or a second level signal or applying a high impedance to said common input/output terminal according to said control signals;
and
a data write-in buffer having a latching function and operatively connected between said common input/output terminal and said memory cell;
said column circuit further comprising:
first means, operatively connected to said data output buffer and operatively connectable to receive said column driving signals, for generating an output disable signal and for causing said data output buffer to generate a high impedance control signal for causing said three-state circuit to apply the high impedance state, in response to one of said column driving signals;
and
second means, operatively connected to said common input/output terminal and to said data write-in buffer, for latching said write data applied to said common input/output terminal into said data write-in buffer after said three-state circuit has applied said high impedance state, in response to another one of said column driving signals.

6 more elements

A semiconductor memory device, operatively connectable to receive write data, a row address strobe signal, a column address strobe signal and a write enable signal, comprising:

a memory cell for storing the write data and for generating read data;
a row enable buffer, operatively connectable to receive the row address strobe signal, for generating a row enable signal in dependence upon the row address strobe signal;
a column enable buffer, operatively connected to said row enable buffer and operatively connectable to receive the column address strobe signal, for generating a column enable signal in dependence upon the row enable signal and the column address strobe signal;
an output disable buffer, operatively connected to said column enable buffer and operatively connectable to receive the write enable signal, for generating an output disable signal in dependence upon the column enable signal and the write enable signal;
an AND gate, operatively connected to said output disable buffer and operatively connectable to receive the write enable signal, for generating an output signal in dependence upon the write enable signal and the output disable signal;
a write enable buffer, operatively connected to said column enable buffer and said AND gate, for generating a driving signal in dependence upon the column enable signal and the output signal;
a data output buffer, operatively connected to said output disable buffer, said column enable buffer and said memory cell, for generating control signals in dependence upon the output disable signal, the column disable signal and the read data;
a three-state circuit, operatively connected to said data output buffer, for generating output data or applying a first impedance level in dependence upon the control signals;
an input/output terminal, operatively connected to said three-state circuit and operatively connectable to receive the write data, for passing therethrough the write data and the output data;
and
a dynamic data write-in buffer, operatively connected to said input/output terminal, said column enable buffer, said write enable buffer and said memory cell, for passing therethrough the write data in dependence upon the column enable signal and the driving signal, so that when the write data is passed through said dynamic data write-in buffer said three-state circuit applies the first impedance level.

8 more elements

A semiconductor memory device, operatively connectable to receive write data, a row address strobe signal, a column address strobe signal and a write enable signal, comprising:

a memory cell for storing the write data and for generating read data;
a row enable buffer, operatively connectable to receive the row address strobe signal, for generating a row enable signal in dependence upon the row address strobe signal;
a column enable buffer, operatively connected to said row enable buffer and operatively connectable to receive the column address strobe signal, for generating a column enable signal in dependence upon the row enable signal and the column address strobe signal;
a latching circuit, operatively connected to said column enable buffer and said row enable buffer, for generating a latched column enable signal in dependence upon the column enable signal and the row enable signal;
a write enable buffer, operatively connected to said latching circuit and to said row enable buffer and operatively connectable to receive the write enable signal, for generating a driving signal in dependence upon the latched column enable signal, the row enable signal and the write enable signal;
a data output buffer, operatively connected to said column enable buffer, said row enable buffer and said memory cell, for generating control signals in dependence upon the column enable signal, the row enable signal and the read data;
a three-state circuit, operatively connected to said data output buffer, for generating output data or applying a first impedance level in dependence upon the control signals;
an input/output terminal, operatively connected to said three-state circuit and operatively connectable to receive the write data, for passing therethrough the write data and the output data;
and
a dynamic data write-in buffer, operatively connected to said input/output terminal, said write enable buffer, said row enable buffer and said memory cell, for passing therethrough the write data in dependence upon the row enable signal and the driving signal, so that when said write data is passed through said dynamic data write-in buffer said three-state circuit applies the first impedance level.

7 more elements

Dependencies are inferred from the claim text.