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AssigneeMobay Chemical Corporation
InventorsRobert N. Hunt, George N. Ong
Estimating the term…
An electrically programmable memory cell comprises two terminals, a unidirectional and/or controllable semiconductor device having anode and cathode regions and a programmable resistor, said anode and cathode regions of the semiconductor device and the programmable resistor being connected in series between the terminals. The programmable resistor comprises a mixture of finely divided metallic material dispersed in a thermoplastic resin. The programmable resistor is initially substantially nonconductive (having a resistivity, for example, in excess of 1 mega ohms per cubic cm). By forcing a sufficient current through the terminals for a period of time, the resistance of the programmable resistor drops drastically to the extent that it may be considered a conductor (having a resistivity, for example, of less than 100 ohms per cubic cm). The programmable resistor may be returned to its substantially nonconductive condition by heating to a temperature above which the memory cell is normally used and below which the semiconductor device is damaged. The semiconductor device may be a transistor, for example, a field effect transistor, a diode or the like.
A memory cell comprising first and second terminals, a semiconductor device having an anode and cathode region, an erasable programmable resistor, said anode and cathode regions of the semiconductor device arranged in series with said erasable programmable resistor between the first and second terminals, said erasable programmable resistor comprising a mixture of finely divided conductive metallic material dispersed in a thermoplastic resin wherein
A memory array comprising a plurality of word lines, a plurality of bit lines, at least one common line, a plurality of memory cells each comprising an erasable programmable resistor and a transistor having a gate and input/output terminals, said gate terminal being coupled to one of said word lines, said input/output terminals being connected in series with said erasable programmable resistor to couple one of said bit lines to said common line and voltage means for applying a voltage to at least one of said bit lines of sufficient magnitude to cause said erasable programmable resistor to become conductive and remain conductive in the absence of additional voltage, and wherein said erasable programmable resistor may be rendered substantially nonconductive by heating to a temperature in excess of the normal use temperature of said erasable programmable resistor for a sufficient period of time.
A memory array comprising a plurality of word lines, a plurality of bit lines and a plurality of memory cells, each memory cell coupled between one of said word lines and one of said bit lines and each memory cell including an erasable programmable resistor in series with a diode whereby voltages of sufficient magnitude may be applied to selected word and bit lines of said array to cause a flow of current in said erasable programmable resistor until it becomes conductive and remains conductive in the absence of additional current, and wherein said erasable programmable resistor may be rendered substantially nonconductive by heating to a temperature in excess of the normal use temperature of said erasable programmable resistor for a sufficient period of time.
Dependencies are inferred from the claim text.