Adapter for interfacing between two buses
AssigneeNCR Corporation
InventorRichard S. Grau
Life of this patent
Estimating the term…
Abstract
An asynchronous interface adapter for interfacing two bidirectional data buses. Data transfer between buses may occur simultaneously with provision made for storing bus data from a first bus until a receiver on the second bus is available. The adapter provides bus requests and grant logic, parity checking, time of day clocking, and is adapted to handle variable-length bus messages with the message bytes being carried in a bit-parallel byte-serial form, asynchronously and generally in a bidirectional manner.
Claims13
An adapter for coupling a data bus to a peripheral data bus, said data bus and said peripheral data bus being bidirectional, and said adapter having the capability of storing messages received from either bus comprising:
- a first buffer memory operatively connected between said data bus and said peripheral data bus for communicating data from said data bus to said peripheral data bus;
- second and third buffer memories operatively connected between said peripheral data bus and said data bus for communicating data from said peripheral data bus to said data bus;
- control means operatively coupled to each buffer memory for controlling the storage and transmission of data to and from said buffer memories;
- and
- clock means operatively coupled to said second and third buffer memories for providing a time tag to each message stored in said second and third buffer memories.
An interface adapter for interfacing between a processor and a peripheral device, said interface adapter being coupled to said processor with a data bus and to said peripheral device with a peripheral data bus, said interface adapter comprising:
- a first buffer memory coupled to said peripheral data bus and to said data bus and capable of storing a plurality of variable length data blocks;
- means operatively coupled to said first buffer memory for sensing the presence of a preselected number of stored data blocks in said first buffer memory and for initiating a service request condition in the processor coupled to said data bus when said preselected number is sensed;
- means operatively coupled to said means for sensing and to said peripheral data bus for denying access to said first buffer memory from said peripheral data bus when the preselected number of data blocks are stored in said first buffer memory;
- control means coupled to said data bus and to said first buffer memory and responsive to control signals from said processor for controlling the transfer of data between said buses;
- means operatively coupled to said first buffer memory for affixing a time signal to each data block received by said first buffer memory;
- and
- a second buffer memory coupled to said peripheral data bus and to said data bus for transferring data from said data bus to said peripheral data bus, said second buffer memory responsive to control signals from said control means for transferring data between said buses.
An adapter for interfacing devices coupled to bidirectional buses comprising:
- first storage means coupled to said buses and operative to receive and transmit data in a first direction;
- second storage means coupled to said buses and operative to receive and transmit data in a second direction;
- means coupled to at least one of said storage means for attaching a time tag to data received by said at at least one of said storage means;
- means coupled to at least one of said storage means for requesting bus access when said at least one of said storage means has acquired a selected number of blocks of data;
- and
- control means operatively coupled to said at least one of said storage means and to said bidirectional buses for effecting a transfer of data from a storage means having a selected number of blocks of data to a bidirectional bus.
Dependencies are inferred from the claim text.