Address buffer circuit
AssigneeFujitsu Limited
InventorTomio Nakano
Life of this patent
Estimating the term…
Abstract
An address buffer circuit for comverting an address signal (A.sub.i) of a TTL level into an address signal (A) of a MOS level an its inverted signal (A) comprising: a pre-amplifier (P-AMP) for receiving the address signal having a TTL level; a main amplifier (M-AMP) comprising a flip-flop (FF.sub.3), a circuit for defining the operation of the flip-flop (FF.sub.3); and an output circuit (OUT) comprised of another flip-flop (FF.sub.4) for producing the address signals of a MOS level. In the pre-amplifier, a depletion type transistor (Q.sub.34) is used as a reference constant current source, which is independent of a power supply voltage (V.sub.DD), for the two values of the address signal of a TTL level.
Claims8
An address buffer circuit, operatively connectable to receive an address signal of a TTL level and a first clock signal, for converting said address signal of the TTL level into an address signal of a MOS level and its inverted signal, comprising:
- first and second power supplies;
- a pre-amplifier, operatively connected to said second power supply and having outputs, for receiving the address signal of a TTL level;
- a main amplifier, operatively connected to the outputs of said pre-amplifier, having first and second inputs and having outputs and comprising a first flip-flop having a first terminal operatively connected to said first power supply and having a second terminal;
- a defining circuit, operatively connected between said first and second power supplies and to said second terminal of said first flip-flop, for defining the potential of said second terminal of said first flip-flop;
- and
- an output circuit, operatively connected to outputs of said main amplifier and comprising a second flip-flop, for producing the address signal of the MOS level and its inverted signal;
- wherein said pre-amplifier comprises:
- a first transistor of an enhancement type having a drain operatively connected to the first input of said main amplifier, having a source and having a gate operatively connectable to receive the first clock signal;
- a second transistor of an enhancement type having a drain operatively connected to the source of said first transistor, a source operatively connected to said second power supply and a gate operatively connectable to receive said address signal of a TTL level;
- a third transistor of an enhancement type having a drain operatively connected to the second input of said main amplifier, having a source and having a gate operatively connectable to receive said first clock signal;
- and
- a fourth transistor of a depletion type having a drain operatively connected to the source of said third transistor, and having a gate operatively connected to a source of said fourth transistor and to said second power supply.
Dependencies are inferred from the claim text.