US 4,395,812 A · Forming an integrated circuit

Abstract

A high performance JFET structure and process are disclosed which are compatible with high performance NPN transistors. The high performance JFET is merged in a bipolar/FET device which forms a dense, two level logic function. The JFET can be employed as a switched device or as an active load in a bipolar logic circuit and is formed in the P-type base diffusion of what would otherwise have been an NPN transistor. In the BIFET merged device, the JFET and bipolar transistor share a common base and drain and a common collector and gate in the P-type base region of what would otherwise have been an NPN transistor. Both an NPN type BIFET and an PNP type BIFET are disclosed. The merged JFET and bipolar transistor provide better than a 30% area reduction when compared to their non-merged precursors.

Claims5

Dependent claims

In a process for forming an integrated circuit having a plurality of P-type regions formed in the same process step, a first subplurality of which are P-type base regions of vertical NPN transistors, a process for forming JFET device in one of the second subplurality of said plurality of P-type regions, comprising the steps of:

forming an insulating layer on the surface of said base region having first and second windows therein;
simultaneously forming first and second spaced apart N-type regions in said base region through said first and second windows for the JFET source and drain;
and
ion implanting an N-type channel region in said base region connected to said source and drain regions;
said P-type base region serving as the gate for the JFET device;
whereby a JFET device may be formed in the base region of an NPN transistor.

3 more elements

Dependencies are inferred from the claim text.

Forming an integrated circuit

Life of this patent

Forming an integrated circuit

Life of this patent

Abstract

Claims5