US 4,395,767 A · Interconnect fault detector for LSI logic chips

Abstract

A large-scale integrated circuit (LSI) chip has an individual voltage level sensing circuit connected with each input and output connecting pin so that isolation between the pins is maintained and so that the individual level sensor output can provide an indication of an abnormal voltage on the input/output pin. The outputs of all level sensors for all input and output pins is connected in common to the input of a comparator circuit. The comparator circuit has a fault detection threshold voltage input and provides a fault indication output signal whenever the voltage input from the level sensor circuits is outside of the detection threshold voltage range. A number of logic chips will have particular input/output pins connected together in a circuit in conventional applications. An open circuit anywhere in the interconnected network will cause some number of input/output pins dependent on the fault location to be pulled out of the detection threshold voltage range. Similarly, any short circuit to ground condition will also cause a voltage shift outside of the detection threshold voltage range. Further, interconnect faults which result in impedance mismatch and cause a "ringing" signal voltage outside of the threshold detection voltage range, will also be detected as a fault signal. Thus, the fault detection system of the present disclosure will detect a number of types of faults in interconnection networks of various logic chips.

Claims9

Dependent claims

A logic circuit interconnect fault detection system comprising:

a first logic circuit chip containing conventional logic circuits connected with input and output pins,
at least one voltage level sensing circuit on said first logic circuit chip associated with one of the connecting pins of said first logic circuit chip,
a comparator on said first logic circuit chip having a first input connected with the output of said voltage level sensing circuit, having a second input for receiving a reference voltage as the fault detection threshold input and the output of said comparator connected to an output pin of said first logic circuit chip, said comparator output being a fault indication signal,
a second logic circuit chip containing conventional logic circuits connected with input and output pins,
at least one voltage level sensing circuit on said second logic circuit chip associated with one of the connecting pins of said second logic circuit chip,
a comparator on said second logic circuit chip having a first input connected with the output of said voltage level sensing circuit, having a second input for receiving a reference voltage as the fault detection threshold input and the output of said comparator connected to an output pin of said second logic circuit chip said comparator output being a fault indication signal,
a plurality of interconnect systems between particular input and output pins of said first and second chips, at least one interconnect system including at least one pin on said first or second chip having a voltage level sensing circuit and
a termination impedance for each interconnect system said impedance having a termination reference voltage level.

5 more elements

An interconnect fault detection system comprised of:

a plurality of circuit boards 1 through N each containing a plurality of logic chips 1 through M,
each of said logic chips containing a plurality of level sensors, one of which is connected to each input and output pin and at least one comparator having a first input connected to the outputs of said level sensors and a second input for connection to a reference voltage, the output of said comparator being provided to a fault output of said chip for indicating that at least one of said level sensors is outside the reference voltage input so that each chip has at least one fault indication output,
an OR means on each board connecting all of the fault indicating outputs of each chip on the board to at least one OR gate which provides a fault indication for the particular board,
a pulse catcher means connected to the individual fault outputs of each logic board,
a status register connected with the output of the pulse catcher, and
a maintenance system providing for diagnostic surveillance of the circuit boards in a logic system so that the status register will give an individual unique indication for each circuit board having an output fault indication.

3 more elements

Dependencies are inferred from the claim text.

Interconnect fault detector for LSI logic chips

Life of this patent

Interconnect fault detector for LSI logic chips

Life of this patent

Abstract

Claims9