Memory device utilizing shift registers for data accessing
AssigneeNippon Electric Co., Ltd.
InventorShigeki Matsue
Life of this patent
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Abstract
A memory device which is effectively utilized as serial access memory with variable shift length of stored data is disclosed. The memory device comprises memory cells arrayed in a matrix form, a shift register whose output is used for selecting memory cells and control means for varying shift length of the shift register.
Claims13
A memory device comprising memory cell array including a plurality of memory cells arrayed in rows and columns, a first shift register having a full shift length and having a plurality of outputs, the number of said outputs of said first shift register being not less than the number of said rows, first means responsive to a start signal for initializing the outputs of said first shift register so as to set only one output among the outputs of said first shift register at a selection level, second means responsive to the outputs of said first shift register for selecting one of said rows, third means for generating a shift length designation signal for designating a desired shift length which is shorter than said full shift length whereby a portion of said shift register outputs corresponding to said desired shift length will address a portion of said rows of said cell array, fourth means for supplying said first shift register with a train of shift signals to thereby shift a location of the set output of said first shift register, fifth means coupled to said third means and said fourth means for detecting when the location of said set output of said first shift register reaches a position of said first shift register corresponding to said desired shift length designated by said shift length designation signal, and sixth means coupled to said first means and said fifth means for producing said start signal upon the detection by said fifth means that said set output of said first register has reached said position corresponding to said desired shift length, whereby said portion of the rows of said cell array are sequentially addressed in synchronism with said shift signals.
A memory device comprising a memory cell matrix including a plurality of memory cells arrayed in rows and columns, a first shift register whose outputs are used to designate one of said rows, a second shift register whose outputs are used to designate one of said columns, first means responsive to a start signal for initializing said first shift register so as to set only one of the outputs of said first shift register at a selection level, second means responsive to said start signal for initializing said second shift register so as to set only one of the outputs of said second shift register at the selection level, means for producing a train of first shift pulses, means for supplying said first shift register with said shift pulses, means responsive to a full shift of said first shift register for producing a second shift pulse, means for supplying said second shift register with said second shift pulse, generating means for generating shift length data for determining a stop position of the outputs of said first shift register which address a portion of said rows of said matrix, means for detecting when said selection level output of said first shift register reaches said stop position, said detecting means producing a detection signal upon detection that said selection level output of said first shift register has reached said stop position and means responsive to said detection signal for generating said start signal so as to return the position of the selection level from said stop position to the set output initialized by said first means, whereby a desired portion of the rows of said matrix from the initialized position of the said output to the stop position of said first shift register are sequentially addressed in accordance with the first shift pulses.
A memory device comprising a memory cell matrix including a plurality of memory cells arrayed in rows and columns, a first shift register whose outputs are used to designate one of sad rows, a second shift register whose outputs are used to designate one of said columns, first means responsive to a start signal for initializing said first shift register so as to set only one of the outputs of said first shift register at a selection level, second means responsive to said start signal for initializing said second shift register so as to set only one of the outputs of said second shift register at the selection level, means for producing a train of first shift pulses, means for supplying said first shift register with said shift pulses, means responsive to a full shift of said first shift register for producing a second shift pulse, means for supplying said second shift register with said second shift pulse, a programmable memory for generating shift length data for determining a stop position of the outputs of said first shift register which address a portion of said rows of said matrix, means for detecting when said selection level output of said first shift register reaches said stop position, said detecting means producing a detection signal upon detection that said selection level output of said first shift register has reached said stop position and means responsive to said detection signal for generating said start signal so as to return the position of the selection level from said stop position to the set output initialized by said first means, whereby a desired portion of the rows of said matrix from the initialized position of the said output to the stop position of said first shift register are sequentially addressed in accordance with the first shift pulses.
A memory device comprising a memory cell matrix including a plurality of memory cells arrayed in rows and columns, input means for receiving analog input data signals and converting said analog data input data signals to digital input data signals to be written into a selected memory cell, output means for receiving digital output data signals derived from a selected memory cell and converting said digital output data signals to analog data output signals, a first shift register whose outputs are used to designate one of said rows, a second shift register whose outputs are used to designate one of said columns, first means responsive to a start signal for initializing said first shift register to set only one of the outputs of said first shift register at a selection level, second means responsive to said start signal for initializing said second shift register so as to set only one of the outputs of said second shift register at the selection level, means for producing a train of first shift pulses, means for supplying said first shift register with said shift pulses, means responsive to a full shift of said first shift register for producing a second shift pulse, means for supplying said second shift register with said second shift pulse, generating means for generating shift length data for determining a stop position of the outputs of said first shift register which address a portion of said rows of said matrix, means for detecting when said selection level output of said first shift register reaches said stop position, said detecting means producing a detection signal upon detection that said selection level output of said first shift register has reached said stop position and means responsive to said detection signal for generating said start signal so as to return the position of the selection level from said stop position to the set output initialized by said first means, whereby a desired portion of the rows of said matrix from the initialized position of the said output to the stop position of said first shift register are sequentially addressed in accordance with the first shift pulses.
Dependencies are inferred from the claim text.