Buffer memory control system of the swap system
AssigneeFujitsu Limited
InventorMasanori Takahashi
Life of this patent
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Abstract
In a buffer memory for a swap data block storage system, in the writing of data in an area of a size equal to or an integral multiple of a block of the buffer memory, when it is detected that a block including an address at which data to be written does not exist in the buffer memory, data is written in a replace block of the buffer memory directly without conducting at least an operation of moving out a block from a main memory.
Claims3
A control system for writing data in a buffer memory of a swap type data block storage system which control system performs an ordinary memory access only with the buffer memory and when data having a requested address does not exist in a data block of the buffer memory, moves out from the buffer memory a selected one of replaceable data blocks thereof to a main memory and moves from said main memory into the buffer memory a data block from the main memory which includes the data at the requested address, said control system comprising:
- a first detecting means for detecting whether the data block of the buffer memory including the data of the requested address exists in the buffer memory;
- and p1 a second detecting means for detecting whether the replaceable data block has been changed after being previously loaded in the buffer memory;
- including means for writing data in the buffer memory in an area of a size equal to or an integral multiple of the data block of said buffer memory when it is detected by said first detecting means that the data corresponding to said requested address does not exist in the buffer memory and it is detected by said second detecting means that the replaceable data block has not been changed, wherein data including the data to be written in is written in the replaceable data block of the buffer memory directly without performing at least the operation of moving in the requested address block from the main memory including data at the requested address so that the data in the replaceable block is overwritten with the data for the requested address.
A buffer memory and control system for said buffer memory operatively connected to a processing unit, which processing unit generates a request signal and data to be written, and to a main memory storing move-in data, comprising:
- a data memory, operatively connected to the processing unit and to the main memory, for storing data used by and generated by the processing unit and for selectively outputting the data in dependence upon the request signal;
- p1 a tag memory, operatively connected to the processing unit, for storing tag signals indicating whether data needed by the processing unit is stored in said data memory;
- a change memory, operatively connected to the processing unit, for storing change signals indicating whether data stored in said data memory has been changed by the processing unit;
- a replace memory, operatively connected to the processing unit, for storing replace signals that indicate whether data stored in said data memory can be replaced;
- write control means, operatively connected to said processor, to said tag memory, to said change memory, to said replace memory and to said data memory, for controlling where data is stored in said data memory in dependence upon the request signals, the tag signals, the change signals and the replace signals;
- and
- a write control circuit, operatively connected to the processing unit, to the main memory and, to said tag memory, to said change memory, to said replace memory, to said data memory and to said write control means, for controlling the storing of the move-in data from said main memory in said data memory in dependence upon the tag signals, the change signals and the replace signals,
- wherein when said tag signals indicate that data requested by the processing unit is not in said data memory, when said replace signals indicate that data stored in said data memory can be replaced, when said change signals indicate that data stored in said data memory has not been changed and when the data to be written in the data memory by the processing unit is equal to or is an integral multiple of the size of a block, the data to be written replaces the data that can be replaced without moving in the move-in data, wherein said tag signals, said replace signals and said change signals are produced in parallel by the respective said tag memory, said replace memory and said change memory.
Dependencies are inferred from the claim text.