Accelerator processor for a data processing system

In a digital data processing system including central processing means for executing instructions and for connection to memory means for storing instructions that include operation codes representing operations to be performed and operand specifiers that indicate the operands on which the operations are to be performed and wherein the central processing means includes addressable register means for storing information including operands, retrieval means for retrieving operands in response to the operand specifiers, code means for generating operation code signals that identify an operation to be performed with respect to at least one operand in accordance with an operation code of an instruction, and processor means connected to the retrieval means and the code means for either processing the retrieved operands in response to certain operation code signals or entering an alternate state of operation in response to predetermined ones of said operation code signals, said processor means including destination computation means for computing a destination address in said memory means at which a result is to be stored and for generating a destination ready signal for indicating that said central processing means is ready to receive a result of at least one operand processed in response to said predetermined operation code signals, a special instruction processing means for processing predetermined ones of the instructions corresponding to said predetermined operation codes, said special instruction processing means including:

• A. operand means for retrieving each operand concurrently with the retrieval thereof by the retrieval means in the central processing means,
• B. special processing means connected to said operand means and operable to process the operands;
• C. control means connected to the central processing means and said special processing means for receiving each of the operation code signals from the code means concurrently with the processor means in the central processing means, for recognizing said predetermined code signals, for operating said special processing means to process the operands in said operand means in response to said predetermined operation code signals, and for automatically disabling the processing of the retrieved operands by the processor means in accordance with said predetermined operation codes when said control means receives one of the predetermined operation code signals but permitting said destination computation means to compute said destination address, and
• D. transfer means connected to said special processor means for transferring to the central processing means the result of the operation by said special processing means in response to said destination ready signal.