Processor implemented communications interface having external clock actuated disabling control

A communications interface adapted to interconnect a system processor and at least one peripheral device, the system processor and the interface being operatively connected to a serial communications bus, the system processor including system clock means for transmitting a system clock signal on the communications bus, the system processor including means for receiving a series of data within time frames defined by and synchronous with the system clock signal, the interface comprising:

• (a) processing means, the processing means having an average instruction execution time sufficiently long with respect to the system clock cycle time wherein the processor's average instruction execution time will not permit data to be transmitted from the processing means to the system processor within the time frame and synchronously with the system clock;
• (b) buffer means operatively connected between the processing means and the communications bus for temporarily storing data being transmitted from the processing means to the system processor, the buffer latching data transmitted by the processing means onto the communications bus data line;
• (c) means, operatively connected to the processing means, for receiving the system clock signal;
• (d) means for transmitting a command signal from the processing means to the clock signal receiving means, the command signal being transmitted after transmission of data to the buffer means by the processing means, said transmission of data occurring during execution of a data transmission routine by the processing means;
• (e) the clock signal receiving means in response to the concurrence of a predesignated portion of the system clock cycle and assertion of the command signal generating a disabling signal, the processing means receiving the disabling signal and in response thereto pausing in execution of the data transmission routine, the clock signal receiving means discontinuing the disabling signal in response to a subsequent occurrence of the predesignated portion of the system clock cycle, and the processing means continuing the execution of the data transmission routine in response to the discontinuence of the disabling signal, whereby the interface operatively controls a data transfer to the sytem processor in synchronism with the system clock.