High speed integrating analog-to-digital converter

In an analog-to-digital converter which includes an integrator that integrates an input signal for a predetermined time period and is then discharged at a known rate until its output passes zero, and a digital clock having a predetermined pulse width for measuring the time taken for the integrator to discharge to zero, wherein the point at which the integrator output crosses zero is detected as occurring on a clock pulse after the actual zero crossing, wherein the measured discharge time is a first discharge time period, the improvement for more accurately measuring the actual discharge time, comprising:

• first means for multiplying the residual output of the integrator, at the time when zero crossing is detected, by a predetermined amount, and for causing the integrator output to change to a level equivalent to said multiplied value of the residual output;
• control means for controlling the operation of the first means and for causing the integrator to discharge for a second measured discharge time period until a second zero crossing is detected;
• and
• combining means for arithmetically combining the second time period with the first time period, thereby obtaining a time measurement which is a more accurate measure of the actual discharge time of said integrator.

In an integrating analog-to-digital converter of the type in which an integrator is charged to a level established by an unknown input signal during an integrate cycle of fixed time and is then deintegrated for an initial time period until a zero crossing is detected, wherein the deintegration time is measured by clock pulses occurring at predetermined intervals, the time to zero crossing being indicative of the magnitude of said unknown input signal, there being a time measurement error introduced because zero crossing is not detected until the occurrence of a clock pulse after actual zero crossing, the improvement for reducing said error, comprising:

• feedback means, operative after said zero crossing is detected, for charging said integrator to a level that is a fixed multiple of the overshoot residual output of the integrator at the time of said clock pulse occurrence after actual zero crossing is detected;
• subsequent deintegration means, operative after the integrator has been charged by the feedback means, for subsequently deintegrating said integrator until a second zero crossing is detected and for measuring the time taken for said subsequent deintegration, said measured subsequent deintegration time being proportional to said time measurement error;
• and
• combining means for arithmetically combining the measured subsequent deintegration time with the measured initial deintegration time period thereby to obtain an error corrected measurement time which is more closely indicative of the actual magnitude of the unknown analog input signal.

A method for converting an analog signal to a digital value, comprising the steps of:

• integrating an analog signal for a predetermined first time period;
• deintegrating said integrated signal at a known rate until it crosses zero;
• measuring, with a digital clock, a second time period from the beginning of deintegration to a first deintegration point which occurs after the signal has crossed zero;
• multiplying the amount the signal has passed zero at said first detection point by a predetermined amount to obtain a second signal;
• deintegrating said second signal at said known rate until it crosses zero;
• measuring a third time period from the beginning of the deintegration of the second signal to a second detection point which occurs after the second signal has crossed zero;
• and
• arithmetically combining the third time period and the the second time period to thereby obtain a fourth time period which is a more accurate measurement of the actual time taken for said integrated signal to deintegrate to zero;
• wherein the ratio of said first time period to said fourth time period is a digital value that is proportional to said analog signal.

An integrating analog to digital converter comprising:

• an integrator for integrating an analog input signal;
• detection means for detecting when the output of the integrator crosses zero;
• multiplication means for multiplying the output of the integrator by a predetermined amount;
• sample and hold means, connected between said multiplication means and said detecting means, for holding the output of the multiplication means;
• and
• a plurality of switches for controlling interconnections between said integrator, detection means, multiplication means and sample and hold means;
• and
• clock controlled logic means for sequentially operating the switches in the following configurations:
• (a) an integrate mode wherein an analog input signal is integrated by the integrator for a predetermined time period;
• (b) a first deintegrate mode wherein the integrator is discharged for a first time period until its output crosses zero;
• (c) a sample and hold mode for storing the output of the multiplication means upon the occurrence of a clock pulse after the integrator output crosses zero;
• (d) a feedback mode for causing the integrator to assume the stored value of the sample and hold means;
• and
• (e) a second deintegrate mode wherein the integrator is again discharged for a second time period until its output crosses zero;
• means for measuring the first and second time periods;
• and
• means for arithmetically combining the first and second time periods to obtain a digital indication of the magnitude of the analog input signal.