Drive circuit
AssigneeNippon Electric Co., Ltd.
InventorTetsuo Misaizu
Life of this patent
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Abstract
A boot strap type circuit which can raise an output potential up to a power supply voltage irrespective of a condition of an input signal is disclosed. The circuit is characterized by comprising a series circuit coupled between a first end of a capacitor, from which end a boot strapped voltage is derived, and a reference voltage, the series circuit being responsive to transition of the input signal for pulling down a potential at the first end of the capacitor after a predetermined delay from that transition.
Claims26
A circuit comprising a first insulated gate field effect transistor, a drain node of said first transistor being connectable to a drain voltage, a second insulated gate field effect transistor, a source node of said first transistor and a drain node of said second transistor being electrically common, the source node of said second transistor being connectable to a source voltage, a gate node of said first transistor being capacitively coupled to the source node thereof by a capacitance, a signal node, and a control circuit responsive to signal levels at said signal node for making said first transistor and said second transistor conducting and non-conducting, respectively, thereby producing a voltage larger than said drain voltage in absolute value at the gate node of said first transistor, said control circuit including a third insulated gate field effect transistor, having a gate for receiving a signal of substantially the same phase as a signal at said signal node and having a drain connected to the gate node of said first transistor, a fourth insulated gate field effect transistor having a gate for receiving a signal of substantially the same phase as a signal at said signal node and having a drain coupled to a source of said third transistor and a source connectable to the source voltage, a fifth insulated gate field effect transistor having a gate for receiving a signal having a phase opposite that of a signal at said signal node and having a source coupled to the gate node of said first transistor and a drain connectable to the drain voltage, whereby said fifth transistor is conducting for a first level at the signal node, and is non-conducting for the second level at the signal node, said fourth transistor is conducting in response to a second level at said signal node said third transistor is conducting after said fourth transistor becomes conducting.
In a circuit where an output is raised up to a power supply voltage by pulling up a gate potential of an output state transistor higher than the power supply voltage by a boot strap effect derived from one end of a capacitor, the improvement comprising a first transistor having a gate receiving a signal which is in the same phase as an input signal to the circuit and connected between the other end of said capacitor and a reference voltage source, and a series circuit including second and third transistors disposed in series between said one end of the capacitor and said reference voltage source, said third transistor having a gate for receiving a signal which has the same phase as said input signal and said second transistor having a gate for receiving a signal having substantially the same phase as said input signal, whereby a potential drop at said one end of the capacitor is reduced by said series circuit.
A circuit comprising a first node, a second node, a first transistor having a gate coupled to said first node and a source coupled to said second node, capacitor means having one end coupled to said first node and the other end coupled to said second node, switching means responsive to a first level of an input signal for substantially changing a potential at said second node to a reference voltage, and control means in responsive to the first level of said input signal for substantially changing a potential at said first node to the reference voltage with a predetermined delay from a time point when said second node is changed towards the reference voltage by said switching means.
A circuit comprising a first terminal to which a first potential is applied, a second terminal to which a second potential is applied, a first node, a second node, an input terminal, a first insulated gate field effect transistor connected between said first terminal and said second node and having a gate connected to said first node, a capacitor coupled between said first node and said second node, second and third insulated gate field effect transistors each connected between said second node and said second terminal, a first inverter having an input node coupled to said input terminal and an output node, a fourth insulated gate field effect transistor coupled between said first terminal and said first node and having a gate coupled to the output node of said first inverter, a series circuit coupled between said first node and said second terminal, said series circuit including fifth and sixth field effect transistors connected in series, a gate of said sixth transistor being connected to said input terminal, a buffer circuit having an input node coupled to said second node and an output node, and a second inverter having an input node coupled to the output node of said buffer circuit and an output node, gates of said third and fifth transistors being connected to the output node of said second inverter, a gate of said second transistor being connected to said input terminal.
A circuit comprising a first terminal to which a first potential is applied, a second terminal to which a second potential is applied, a first node, a second node, an input terminal, a first insulated gate field effect transistor connected between said first terminal and said second node and having a gate connected to said first node, a capacitor coupled between said first node and said second node, second and third insulated gate field effect transistors each connected between said second node and said second terminal, a first inverter having an input node coupled to said input terminal and an output node, a fourth insulated gate field effect transistor coupled between said first terminal and said first node and having a gate coupled to the output node of said first inverter, a series circuit coupled between said first node and said second terminal, said series circuit including fifth and sixth field effect transistors connected in series, gates of said fifth and sixth transistors being connected to said input terminal, a buffer circuit having an input node coupled to said second node and an output node, and a second inverter having an input node coupled to the output node of said buffer circuit and an output node, a gate of said third transistor being connected to the output node of said second inverter, a gate of said second transistor being connected to said input terminal.
A circuit comprising a first terminal to which a first potential is applied, a second terminal to which a second potential is applied, first and second insulated gate field effect transistors connected in series between said first and second terminals, a first node, a second node, a gate of said first transistor being connected to said first node, an intermediate junction of said first and second transistors being connected to said second node, said first node being capacitively coupled to said second node, a signal node, and a control circuit responsive to signal levels at said signal node for operatively producing a voltage larger than said first potential at said first node, said control circuit including third and fourth insulated gate field effect transistors connected in series between said first node and said second terminal, said fourth transistor being adapted to take a conducting state when a signal level at said signal node makes said second transistor conducting, said third transistor being adapted to take a conducting state after said fourth transistor is turned to conducting.
Dependencies are inferred from the claim text.