Electronic timer
AssigneesMatsushita Electric Works, Ltd., Matsushita Electric Industrial Co., Ltd.
InventorsKenichi Yoda, Hideo Togawa, Eizou Ogawa, Masao Kayahara
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AssigneesMatsushita Electric Works, Ltd., Matsushita Electric Industrial Co., Ltd.
InventorsKenichi Yoda, Hideo Togawa, Eizou Ogawa, Masao Kayahara
Estimating the term…
An electronic timer wherein a counting circuit for counting outputs of a CR oscillating circuit comprises a plurality of partial counting circuits which are cascade-connected with one another, the respective partial counting circuits are automatically reset by an automatic resetting circuit when a source current voltage is applied or reset by an external resetting circuit at a desired time, the outputs of the CR oscillating circuit are counted by the respective partial counting circuits after the resetting, and a following output circuit is driven when the count reaches an externally set value of a setting circuit. The partial counting circuits are divided into groups by an external driving test circuit to quickly test the operation of the counting circuit.
An electronic timer comprising a CR oscillating circuit, a counting circuit including a plurality of partial counting circuits connected in cascade to one another for counting oscillated outputs of said CR oscillating circuit, an output circuit driving an associated following circuit in response to an output selected out of outputs from one of said partial counting circuits in the final stage of said cascade connection, an automatic resetting circuit for automatically resetting said plurality of partial counting circuits of said counting circuit upon an application of a source current, an external resetting circuit for resetting the partial counting circuits in response to an external signal, a test circuit for dividing said plurality of partial counting circuits into a plurality of groups, and a test signal generating circuit for inspecting the function of each of said divided groups by externally driving said test circuit, said external resetting circuit and said test signal generating circuit being formed of a common circuit comprising first and second inverting circuits receiving a common external signal and respectively having a low inverting threshold value and a high inverting threshold value so that, when said external signal reaches only said low inverting threshold value, a signal driving said test circuit will be provided and, when the external signal reaches said high inverting threshold value, an external resetting signal resetting said plurality of partial counting circuits of said counting circuit will be provided.
Dependencies are inferred from the claim text.