Integrated memory module having selectable operating functions

In an integrated memory module of the type in which a plurality of memory cells are arranged in a matrix of columns and rows and are addressable by row and column addresses received via a plurality of address terminals in response to strobe signals to provide data on a plurality of write/read lines, in which a bidirectional address buffer is connected to the address terminals for receiving an address, and in which a row address decoder and a column address decoder are connected between the address buffer and the rows and columns of memory cells, respectively, for producing row and column selection signals, the improvement therein comprising:

• a data bus connected to said memory and having a plurality of lines equal to the number n of write/read lines to be selected by a higher value portion of a column address;
• a mode register operable to receive and store mode signals from and to provide mode signals for the address terminals, the mode signals defining the operating functions of the memory module, in response to predetermined control signals;
• a bidirectional data input and data output device connected to said data bus;
• said memory matrix divided into small n areas each including an identical plurality of columns of memory cells and all said areas being simultaneously accessible;
• and
• a switch circuit, including a bidirectional operating portion, and selectively operable to connect the address buffer to the address decoders, to connect the address buffer to the mode register and to connect the address register to the data bus in response to receipt of other control signals including the strobe signals.