Decoding and selection circuit for a monolithic memory

A selection circuit for a memory array having a matrix of cells arranged in n rows and m columns wherein the cells of different rows are connected to n word lines, the selection of a word line being controlled by an address decoding circuit receiving at its input a line addressing signal and having n outputs, each output controlling the state of a line driver transistor, the n driver transistors each being of the NPN type, each of which includes a collector, an emitter and a base, said collector being connected to a voltage supply terminal, said emitter being connected to a word line and said base being connected to an output of said decoding circuit, comprising;

• n control transistors each being of the PNP type, each of said control transistors being associated with one of said driver transistors and having an emitter connected to said voltage supply terminal and a collector connected to the base of its associated driver transistor, and
• means for supplying a current to the control electrode of each of said control transistors, said means including a regulating transistor having a conductivity type similar to that of said control transistors and connected so as to form a current mirror with said control transistors, said regulating transistor having its base connected to the base of at least one of said control transistors, its emitter connected to said voltage supply terminal and its collector connected to its base and to a controllable current source.