Low power storage cell

A dual low power storage cell operable in an access mode and a storage mode and comprising,

• a flip-flop circuit having first and second transistors, a first terminal of each of said transistors being connected to cell ground potential, a second terminal of each of said transistors being connected to cell supply voltage, a third terminal of said first transistor being connected to the second terminal of said second transistor and a third terminal of said second transistor being connected to the second terminal of said first transistor,
• first and second voltage sources,
• first switch means operatively connected to said first voltage source and to said second terminal of said first and second transistors and effective when in an "on" state to place the storage cell in the access mode by applying a supply voltage of a first voltage level to said flip-flop circuit,
• second switch means operatively connected to said second voltage source and to said second terminal of said first and second transistors for placing the storage cell in a storage cell in the storage mode by applying a supply voltage of a second voltage level to said flip-flop circuit, said second voltage level being substantially less than said first voltage level, and
• means for placing said first switching means in an "off" state, thereby removing said first voltage level from said flip-flop circuit, when the storage cell is in its said storage mode.