US 4,394,731 AGranted

Cache storage line shareability control for a multiprocessor system

AssigneeInternational Business Machines Corporation

InventorsFrederick O. Flusche, Richard N. Gustafson, Bruce L. McGilvray

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Abstract

A multiprocessor (MP) system is described having central processors (CPs) in which each CP has a store-in-cache (SIC) with an associated processor directory (PD). Each PD has a plurality of line entries which define the content of corresponding line positions in the associated SIC. Each line entry has an associated data shareability control bit, designated EX, which may be set to a one or zero state to indicate, respectively, the exclusive (EX) or readonly (RO) state of the associated line. An exclusive line is not shareable, but a readonly line is shareable i.e. may exist validly in more than one SIC in the MP. Any CP in the MP can request data in an EX state from its SIC, which data may or may not be found in its SIC or in another CP's SIC. If a CP requests a line of storage data in EX state and the line is found in EX state in another CP's SIC, it may be allowed to remain in the other CP's SIC by being set to RO state in both CPU SICs for the situations in which: (1) the line is found unchanged in EX state in the other CP's SIC, or (2) the line is found in RO state in the other CP's SIC, in which case the line is received and set to RO state in the requesting SIC even though requested in EX state. But if the line is found to be changed in the other CP's SIC, its shareability designation in the requesting SIC will be EX and the line is invalidated in the other CP's SIC from where it is castout.

Claims16

Dependent claims

A multiprocessor (MP) system having at least two processors, in which each processor has a processor store-in-cache, and a processor cache directory (PD) with a plurality of line entries for corresponding line positions in the associated cache, the MP system further comprising,

each processor requesting its PD for main storage access with either an exclusive (EX) or readonly (RO) shareability signal,
an exclusive (EX) bit position, a line change (CH) bit position, a valid (V) bit position, and an address field being provided in each PD line entry, the opposite states of the EX bit position indicating exclusive or readonly shareability for the corresponding line position,
cache miss detecting means connected to each PD for generating a storage line fetch and cross-interrogation (XI) command from each cache miss, the XI command indicating if the initiating processor request has an exclusive or readonly signal and is a fetch or store request and indicating a main storage address for the request,
cross-interrogation (XI) means connected to receive each XI command,
control means connected to receive the output of the XI means and searching valid line entries represented in each other PD in the MP system for detecting any existing conflicting line having the main storage address indicated in the XI command,
testing means associated with each PD and connected to receive each XI command for testing the state of the EX bit position in any entry found to represent a conflicting line, and if the EX bit is set to the exclusive state also testing the CH bit for the conflicting line,
means connected to each cache for casting out any conflicting line from the associated cache if the testing means senses the CH bit is on, and setting off the V bit position in the associated PD entry for the conflicting line,
means in the associated PD for the conflicting line for setting the EX bit position to the readonly state if the CH bit position is off and not casting out the line which then remains valid in its processor cache,
inter-cache means connected between the processors in the MP for setting an EX bit position to readonly state in a line entry for the storage line fetch in the PD which generated the XI command when the EX bit position in each entry for the conflicting line is set to readonly state,
whereby readonly cache sharing is permitted for the line obtained by the storage line fetch found to have a conflicting line in another cache in a non-changed state, even though the initiating processor request is for exclusive control of the requested data.

7 more elements

A MP system having at least two processors, in which each processor has a processor store-in-cache, and a processor cache director (PD) with a plurality of line entries for corresponding line positions in the processor cache, the MP system further comprising,

each processor having request means signalling if the processor exclusively requests its PD for a fetch or store access of its cache,
an exclusive (EX) bit position, a line change (CH) bit position, a valid (V) bit position, and an address field being provided in each line entry in each PD, means for setting the EX bit position in the assigned line position to exclusive state in response to an exclusive request from the associated processor,
PD line request means connected to each PD for being initiated by a processor request which does not find the requested data in the associated processor cache, means for assigning a line position in the associated PD for the requested line to be fetched,
means connecting a corresponding copy directory (CD) to each PD for a respective processor, each CD line entry having an EX bit position, a V bit position and an address field set to the same values as a corresponding line entry in the related PD,
XI register means connected to each CD for receiving each PD line request identifying the requesting processor, whether the processor request is a fetch or store, the request address, and if requested exclusively or readonly,
XI priority means connected to each CD for each PD line request to initiate all CD control means to search all CDs for any conflicting line entry having the request address and to test the state of the EX bit in any conflicting line entry found in any CD.

3 more elements

Dependencies are inferred from the claim text.