Jump return stack
AssigneeNCR Corporation
InventorRolfe D. Armstrong
Life of this patent
Estimating the term…
Abstract
A jump return stack is provided in a data processor having a plurality of control registers including a fetch control register and an execution control register. The jump return stack comprises a memory stack, an address register, and a counter-register interposed between the memory stack and the control registers of the data processor. The counter-register is always made to store the latest entry into the memory stack, that is the top of the stack, such that the latest entry into the stack is immediately available to the control registers of the data processor thereby eliminating a memory access to the stack.
Claims9
In a data processor comprising control store means to store instructions at specific addresses, fetch control register means connected thereto to control the operation thereof, execution means to process information fetched from the addresses in controllable sequence, jump return stack means comprising:
- storage means for storing a plurality of jump return addresses in order;
- counter means connected to said storage means for addressing said storage means;
- and
- register means connected to said storage means to supply address information thereto and separately connected to said execution means and separately connected to said fetch control register means for storing the latest jump return address inputted to said jump return stack means, to make the latest jump return address available to said fetch control register means independently of receiving a jump return address directly from the storage means.
Dependencies are inferred from the claim text.