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AssigneeThe United States of America as represented by the Administrator of the National Aeronautics and Space Administration
InventorWayne H. Kohl
Estimating the term…
A multiport memory architecture is disclosed for each of a plurality of task centers (11, 20, 30, 40) connected to a command and data bus (10). Each task center, (such as the center 11) includes a memory (13) and a plurality of devices (12, 14, 15, 17) which request direct memory access as needed. The memory (13) includes an internal data bus (53) and an internal address bus (50) to which the devices are connected, and direct timing and control logic (54) comprised of a 10-state ring counter (62) for allocating memory devices by enabling AND gates (64) connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates (66) to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter (14) which serially shifts onto the command and data bus (10) a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.
In a distributed data processing system having a plurality of independent centers connected to a bus for performing tasks, and having a source of system clock pulses applied to all centers, each task center being comprised of a memory and a plurality of devices using said memory, one of said devices in each center being a bus adapter coupling said bus to said memory, and one of said devices in one of said centers being a bus controller for control of the transfer of data between task centers, a separate multiport memory architecture for said memory of each task center comprising logic means responsive to said clock pulses for synchronous timing and control of direct access to said memory by devices of the task center, including said bus adapter, a separate device being given access during each of NX clock pulse periods in a predetermined sequence, with selected devices being given access more than once in a sequence, where N is the fixed number of bits in a word to be serially transferred on said bus between centers and X is an integer selected for each task center to satisfy particular needs of the task center, whereby all devices of a task center are given memory access at least once during NX clock pulse intervals.
A multiport memory comprised of a memory into which data may be stored, and from which data stored may be read out, a bus for data stored and read from said memory, a bus for addressing said memory for storing or reading data, a plurality of devices connected to said address bus and said data bus for access to said memory to read or store, or both read and store data, each device being adapted to generate a request signal when memory access is required, and direct memory access timing and control means for allocating memory access to said devices in a fixed periodic sequence and acknowledging a request by each device during its allocated intervals by an acknowledgement signal to the device requesting access, thereby to enable it to place an address on said address bus and place or accept data on or from said data bus for storing or reading data from said memory.
Dependencies are inferred from the claim text.