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US 4,394,702 AGranted
Power failure detection and control circuit
AssigneeSperry Corporation
InventorGuy Boothe
Life of this patent
Estimating the term…
Abstract
A circuit is provided for detecting a low power condition which is undesirable and effectively turns off a computer system to prevent incorrect operation thereof. The circuit does not turn on the computer system until the correct power condition is achieved. The circuit is also sensitive to the power condition to establish the time duration permissible for causing the computer system to be turned off.
Claims10
A circuit for detecting the condition of a power source comprising,
- a first pulse circuit (1, OS1) for selectively generating pulses (D) of a first time period and frequency as a function of the signal (C) supplied thereto from said power source,
- a second pulse circuit (OS2) for selectively generating pulses (E) of a second time period and frequency as a function of the pulses (D) supplied thereto by said first pulse circuit, said second pulse circuit selectively supplying pulses to said first pulse circuit to effectively disable said first pulse circuit, and
- reset circuit means (2, etc) connected between said power source and each of said first and second pulse circuits to reset said first and second pulse circuits to a prescribed condition when said power source has returned to a prescribed level.
Dependencies are inferred from the claim text.